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參數(shù)資料
| 型號： | FAN5068DDR |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | FAN5068 Component calculation and simulation tools |
| 中文描述： | FAN5068組件的計算和模擬工具 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 159K |
| 代理商： | FAN5068DDR |
PRODUCT SPECIFICATION
FAN5068
14
REV. 1.0.1 9/9/04
Power MOSFET Selection
For a complete treatment of MOSFET selection and
efficiency calculations, see:
AN-6005:
Synchronous buck MOSFET loss calculations
with Excel model.
Losses in a MOSFET are the sum of its switching (P
SW
) and
conduction (P
COND
) losses.
In typical applications, the FAN5068 converter’s output
voltage is low with respect to its input voltage, therefore the
Lower MOSFET (Q2) is conducting the full load current for
most of the cycle. Q2 should be therefore be selected to min-
imize conduction losses, thereby selecting a MOSFET with
low R
DS(ON)
.
In contrast, the high-side MOSFET (Q1) has a much shorter
duty cycle, and its conduction loss will therefore have less of
an impact. Q1, however, sees most of the switching losses,
so Q1’s primary selection criteria should be gate charge.
High-Side Losses:
Figure 12 shows a MOSFET's switching interval, with the
upper graph being the voltage and current on the Drain to
Source and the lower graph detailing V
GS
vs. time with a
constant current charging the gate. The x-axis therefore is
also representative of gate charge (Q
G
). C
ISS
= C
GD
+ C
GS
,
and it controls t1, t2, and t4 timing. C
GD
receives the current
from the gate driver during t3 (as V
DS
is falling). The gate
charge (Q
G
) parameters on the lower graph are either
specified or can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both the
rising edge and falling edge, Q1’s switching losses, occur
during the shaded time when the MOSFET has voltage
across it and current through it.
These losses are given by:
where:
P
UPPER
is the upper MOSFET’s total losses, and P
SW
and
P
COND
are the switching and conduction losses for a given
MOSFET. R
DS(ON)
is at the maximum junction temperature
(T
J
). t
S
is the switching period (rise or fall time) and is t2+t3
(Figure 12).
The driver’s impedance and C
ISS
determine t2 while t3’s
period is controlled by the driver’s impedance and Q
GD
.
Since most of t
S
occurs when V
GS
= V
SP
we can use a
constant current assumption for the driver to simplify the
calculation of t
S
:
Figure 12. Switching Losses and QG
Figure 13. Drive Equivalent Circuit
Most MOSFET vendors specify Q
GD
and Q
GS
. Q
G(SW)
can
be determined as: Q
G(SW)
= Q
GD
+ Q
GS
– Q
TH
where Q
TH
is the gate charge required to get the MOSFET to it’s thresh-
old (V
TH
). For the high-side MOSFET, V
DS
= VIN, which
can be as high as 20V in a typical portable application.
Care should also be taken to include the delivery of the
MOSFET's gate power (P
GATE
) in calculating the power
dissipation required for the FAN5068:
where Q
G
is the total gate charge to reach VCC.
P
UPPER
P
SW
P
COND
+
=
P
SW
V
---------------------
I
L
×
2
2
×
t
S
×
F
SW
=
(10a)
P
COND
V
V
IN
--------------
I
OUT
2
×
R
DS ON
)
×
=
(10b)
V
SP
V
TH
V
GS
t1
t2
t3
4.5V
t4
t5
Q
G(SW)
V
DS
I
D
Q
GS
Q
GD
C
ISS
C
GD
C
ISS
C
GD
R
D
R
GATE
C
GS
HDRV
5V
SW
VIN
G
t
S
Q
I
DRIVER
)
--------------------
Q
R
DRIVER
)
SP
R
GATE
+
------------------------–
------------VCC
≈
=
(11)
P
GATE
Q
G
VCC
×
F
SW
×
=
(12)
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