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參數(shù)資料
| 型號： | FAN5068DDR |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | FAN5068 Component calculation and simulation tools |
| 中文描述： | FAN5068組件的計算和模擬工具 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 159K |
| 代理商： | FAN5068DDR |
PRODUCT SPECIFICATION
FAN5068
16
REV. 1.0.1 9/9/04
the other side connected to the ground plane through a
via. If there is a significant amount of noise on VCC pin,
L-C decoupling at the VCC pin can be used to attenuate
the noise.
4.
The pad under the IC is for power ground return. This
pad needs to be directly connected to the ground plane
by vias under the IC as mentioned above. Do not con-
nect this pad to Pin #19 through the top copper, as this is
the analog ground at the IC.
5.
Use copper planes for power and GND wherever possi-
ble to reduce trace resistance and inductance as well.
6.
Resistors should be as close to the IC pins as possible to
prevent noise pickup due to radiated and adjacent high
dV/dT signals. Avoid routing sense signals near the gate
drive, SW node, boot, or other high dV/dT nodes. Par-
ticular care should be taken to place R3 (ISNS resistor)
as close as possible to pin 11
7.
The closed path (loop) around the feedback components
should be minimized to avoid noise pickup. These com-
ponents will need to be close to the feedback pin. R2,
R10 and C10 should be returned to pin 19 or to the GND
plane as close to pin 19 as possible and away from other
current on the GND plane.
8.
Minimize the path length for the boot cap formed by
SW, C5 and pin 8.
9.
Use thick trace widths for Q1 and Q2 gate drive signals
to minimize their resistance and inductances. Top cop-
per should be used to route the gate drive traces if possi-
ble, especially Q1 Gate to HDRV.
10. Power Plane Routing: The Power Plane routing for
traces carrying higher currents as in the VDDQ output,
need to be routed carefully. The loop from C2 (5V Dual
high frequency bypass cap) to the source of Q2 needs to
be minimized to minimize ringing on SW and Q1 drain.
The loop formed by COUT to the source of the Q2 also
needs to be minimized to keep the ringing on the switch
node low. Basically what we are trying to achieve by
doing this is to reduce the loop inductance and thereby
minimizing the energy in the stray inductance.
This is the
Decoupling Capacitor
Close to VCC Pin
This is the Ground Pin
These are the 5 holes
below the IC for easy
flow soldering
R3 is very
close to ISNS
pin
R5 is very close to ILIM
pin
The Loop
around C6,R6
and C9 is
minimized
The Loop
around
C19,R11 and
R1,R2 is
minimized
- Q2 ON time Current flow path
C13
C14
C16
C20
L1
Q2
Q1
- Q1 ON time Current flow path
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