參數(shù)資料
型號: FAN5068DDR
廠商: Fairchild Semiconductor Corporation
英文描述: FAN5068 Component calculation and simulation tools
中文描述: FAN5068組件的計算和模擬工具
文件頁數(shù): 8/18頁
文件大?。?/td> 159K
代理商: FAN5068DDR
PRODUCT SPECIFICATION
FAN5068
8
REV. 1.0.1 9/9/04
Circuit Description
Overview
Control Functions
S3#I, EN Input Threshold
S3#I EN Input Current
Over-Temperature Shutdown
Over-Temperature Hysteresis
S3#O Output Low R
DS(ON)
S3#O Output High Leakage
SBSW Output Low Resistance
SBSW Sink current (note 1)
SBSW Output High (note 2)
1.0
–1
1.25
1.55
1
V
μA
°C
°C
μA
nA
150
25
170
4
125
500
820
300
10
200
V(S3#O) = 12V
5V MAIN OK
5V MAIN < UVLO
1200
Electrical Specifications
(continued)
Recommended operating conditions, component values per Figure 1 unless otherwise noted.
Parameter
Conditions
Min.
Typ.
Max.
Units
The FAN5068 provides 5 functions:
1.
A general purpose PWM regulator, typically used to gen-
erate VDDQ for DDR memory.
2.
A low-dropout linear VTT regulator capable of sinking
and sourcing 1.5A peak.
3.
An adjustable Ultra Low Drop Out (ULDO) controller
which, in conjunction with an external N-Channel power
MOSFET, provides a programmable low voltage output.
The power source for this output is typically the VDDQ
output and is used to provide the 1.2V GTL
processor FSB termination voltage.
4.
Control for generating a 5V DUAL voltage using an
external N-channel to supply power from 5V MAIN in
S0, and an external P-Channel to provide power from 5V
Standby (5VSB) in S3.
5.
An internal LDO which regulates "3.3V Always" in S3
mode from VCC(VSB). In S3, this regulator is capable
of 1.25A peak currents with average currents limited by
the thermal design of the PCB.
At initial power-up, or when transitioning from S5, the PWM
regulator will be disabled until 5V MAIN is above its UVLO
threshold.
Table 2. ACPI States
STATE
S5
S3
S0
S3#I
X
L
H
EN (S5#)
L
H
H
S3#O
L
L
H
SBSW
H
L
H
VDDQ
OFF
ON
ON
VTT
OFF
OFF
ON
G1.2 LDO 3.3 ALW LDO
OFF
OFF
ON
ON
ON
OFF
STATE
S5
S3
S0
3.3 ALW
LDO
LDO
Q5 (MAIN)
5V Dual
OFF
+5VSB
+5 MAIN
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