PRODUCT SPECIFICATION
FAN5240
REV. 1.0.2 10/10/01
9
Applications Information
Overview
The FAN5240 is a high efciency and high precision DC/DC
controller for AMD Mobile Athlon and Mobile Duron note-
books. It provides the voltage necessary for the processor’s
core. The core voltage is programmed with a 5-bit VID.
Utilization of both input and output voltage feedback, and
voltage-mode compensation, allows for fast loop response
over a wide range of input and output variations. This
scheme has a superior range of output current operation and
is free of the light load instabilities typical of current mode.
The CPU output can be changed while operating, transition-
ing in less than 100sec. The IC design allows for a mini-
mum size design of magnetics and discrete transistors for
minimum cost and space at maximum performance. Active
droop on the CPU output minimizes the number of output
capacitors required, while the two phase architecture mini-
mizes the number of input caps.
Power Architecture
The power output of the FAN5240 is generated from the
unregulated input voltage using a two phase synchronous
buck converter. Both the high-side and the low-side
MOSFETs are N-channels to maximize efciency. The
two phases switch 180° out of phase to minimize input
ripple current.
The power output has a pin for setting output overcurrent;
two pins for true differential remote voltage-sense feedback;
a pin for sensing MOSFET current, used for summing-mode
control; a pin that generates a softstart, and a pin that can be
used to shutdown the converter.
Loop Description
The control loop of the FAN5240 uses summing-mode con-
trol. This means that no external compensation is required.
The control loop measures the current differentially across
the low-side MOSFET, subtracting the drain voltage from
the source voltage. The resulting voltage is proportional to
the output current. It is subtracted from the voltage feedback
signal, and the sum is subtracted from the reference voltage.
The control loop senses the output voltage differentially,
measuring both the output voltage and the ground voltage at
the point of regulation. In addition, the converter uses volt-
age feed-forward to guarantee loop rejection of input voltage
variation: the ramp amplitude is varied as a function of the
battery voltage.
Compensation of the control loop amounts to merely select-
ing suitable output capacitors. Most selections of common
Tantalum or organic capacitors will result in a stable loop
with adequate phase margin.
Load Transient Response
Because of the high input voltage from the battery, and the
low output voltage of the converter, the high-side MOSFET’s
duty cycle is very small. Thus a transient will be likely to
occur during the high-side MOSFET’s off-time. To avoid the
delay of waiting for the next cycle in response to large load
steps, ultra-fast feedback is incorporated into the PWM
scheme. An additional comparator constantly monitors the
output voltage. If the output voltage exceeds the threshold,
the comparator forces the ramp generator to start a new pulse
within the same clock cycle, turning the high-side MOSFET
on at once. With this method, response time to a transient of
about 200nsec is achieved.
The PWM controller has a built-in duty cycle clamp in the
path from the error amplier to the PWM comparator.
During a severe load step, the output signal from the error
amp can go to its rail, pushing the duty cycle to almost 100%
for a signicant amount of time. This could cause a severe
rise in the inductor current, especially at high battery volt-
age, and lead to a long recovery time or even failure for the
converter. To prevent this, the output of the error amplier is
clamped to a xed value after two clock cycles if a large
output voltage excursion is detected. Sensitivity of this
circuit is set in such a way as not to affect the PWM control
during transients normally expected from the load.
Load transient response can be improved by adding droop to
the circuit. This can be easily accomplished with the
FAN5240 by placing a resistor between the COREFB pin
and the output voltage sense point. The amount of droop will
be given by the formula:
where ITOT is the total output current, RDS,on is the resis-
tance of the low-side MOSFETs in one slice, and RS is the
value of the sense resistor attached to pin 6 or 22.
Gate Drive
The gate drive signals provide anti-shootthrough protection.
As MOSFET switching time can vary dramatically from
type to type, gate control logic in the FAN5240 provides
adaptive dead time control by monitoring the gate voltage of
both the high-side and low-side MOSFETs.
Current Sharing
The control architecture of the FAN5240 guarantees that the
two slices of the converter will share current well, typically
to 5%. The limitation to the matching of the two slices’
current is the matching between the low-side MOSFETs
used in the two slices. Differing RDS,on, and differing
temperatures of the MOSFETs, will result in proportionally
differing currents. If precision current sensing is necessary, it
may be accomplished by using a current sense resistor in
series with the source of each slice’s low-side MOSFETs.
The ISNS resistor should then be attached to the source of
the MOSFETs for proper current sensing.
V
Droop
R
Droop
I
TOT
R
DSon
,
2.76R
S
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