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參數(shù)資料
| 型號： | FAN5355MP07X |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.8 A SWITCHING CONTROLLER, 3350 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | 3 X 3 MM, GREEN, MO-229WEED-5, MLP-10 |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 1995K |
| 代理商： | FAN5355MP07X |
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2008 Fairchild Semiconductor Corporation
19
www.fairchildsemi.com
FAN5355 Rev. 1.0.4
FA
N
5355
—
1A
/
0.8A
,3M
hz.
D
igit
a
lly
Prog
rammabl
e
TinyB
u
ck
TM
Regulator
Software Enable
The EN_DCDC bit, VSELx[7] can be used to enable the
regulator in conjunction with the EN pin. Setting EN_DCDC
with EN HIGH begins the soft-start sequence described
above.
EN_DCDC Bit
EN Pin
I
2C
REGULATOR
0
OFF
1
ON
1
0
OFF
0
1
ON
OFF
Table 5. EN_DCDC Behavior
Light-Load (PFM) Operation
The FAN5355 offers both a Normal PFM (NPFM) and
Enhanced PFM (EPFM) mode. NPFM is normally used
when the load current is very low and when quiescent
current must be minimized. EPFM provides more accurate
DC regulation and limits the minimum frequency to 25kHz
typical to prevent operation in the audio band.
VOUT ripple is identical in both modes (less than 20mV), and
both modes feature very fast response to load transients.
The FAN5355 incorporates a single-pulse, light-load
modulation that ensures:
Smooth transitions between PFM and PWM modes
Minimum frequency, of 25kHz typical, to avoid audible
noise (EPFM only)
Single-pulse operation for low ripple
Predictable PFM entry and exit currents.
PFM begins after the inductor current has become
discontinuous, crossing zero during the PWM cycle in 32
consecutive cycles. PFM exit occurs when discontinuous
current mode (DCM) operation cannot supply sufficient
current to maintain regulation. During PFM mode, the
inductor current ripple is about 40% higher than in PWM
mode. The load current required to exit PFM mode is
thereby about 20% higher than the load current required to
enter PFM mode, providing sufficient hysteresis to prevent
“mode chatter.”
While PWM ripple voltage is typically less than 4mVP-P,
PFM ripple voltage can be up to 30mVP-P during very light
load. To prevent significant undershoot when a load
transient occurs, the initial DC setpoint for the regulator in
PFM mode is set 10mV higher than in PWM mode. This
offset decays to about 5mV after the regulator has been in
PFM mode for ~100
μs. The maximum instantaneous
voltage in PFM is 30mV above the setpoint.
In Enhanced PFM (EPFM) mode, the regulator maintains a
minimum frequency of 25kHz (typical) to prevent audible
noise being generated by the external components. To
achieve this, the regulator turns on the low-side MOSFET to
“create demand” for a pulse if no pulse had been required
for 40
μs. The minimum frequency limit circuit takes effect
with load currents below about 3.5mA. Above that load
point, the natural PFM period is less than 40
μs. This circuit
only activates when ILOAD is greater than ~3.5mA. If the load
remains above 3.5mA, there is no quiescent current penalty
for EPFM mode and there is some accuracy advantage.
NPFM allows the switching frequency (fSW) to go as low as
required to support the load current. This achieves a lower
quiescent current than EPFM, but sacrifices up to ±15mV of
DC accuracy when compared to EPFM or PWM modes. As
shown in Table 6, EPFM and NPFM modes have the same
frequency when the load is above 4mA. If the load is above
4mA, EPFM is the preferred mode, since it has tighter DC
regulation with the same efficiency.
EPFM can only be enabled by setting the MODE_CTRL
bits to 11. In versions with MODE_CTRL disabled (see
Table 12
), the PFM mode is NPFM.
Mode
EPFM
NPFM
IQUIESCENT typical at ILOAD = 0
110
μA
38
μA
DC Accuracy
Better
Good
fSW at ILOAD = 0
25 kHz
to 0 Hz
fSW at ILOAD > 3.5mA
> 33 kHz
Table 6. PFM Modes Comparison
bits: CONTROL1[3:0] (see Table 12 for details).
Switching Frequency Control and
Synchronization
The nominal internal oscillator frequency is 3MHz. The
regulator runs at its internal clock frequency until these
conditions are met:
1.
EN_SYNC bit, CONTROL1[5], is set; and
2.
A valid frequency appears on the SYNC pin.
CONTROL2
FSYNC Valid
PLL_MULT
fSYNC Divider
Min.
Typ.
Max.
00
1
2.25
3.00
4.00
01
2
1.13
1.50
2.00
10
3
0.75
1.00
1.33
11
4
0.56
0.75
1.00
Table 7.SYNC Frequency Validation for fOSC(INTERNAL)=3.0MHz
If the EN_SYNC is set and SYNC fails validation, the
regulator continues to run at its internal oscillator frequency.
The regulator is functional if fSYNC is valid, as defined in
Table 7, but its performance is compromised if fSYNC is
outside the fSYNC window in the Electrical Specifications.
When CONTROL1[3:2] = 00 and the VSEL line is LOW, the
converter
operates
according
to
the
MODE0
bit,
CONTROL1[0], with synchronization disabled regardless of
the state of the EN_SYNC and HW_nSW bits.
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