參數(shù)資料
型號(hào)： FAN5355MP07X
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： 1.8 A SWITCHING CONTROLLER, 3350 kHz SWITCHING FREQ-MAX, PDSO10
封裝： 3 X 3 MM, GREEN, MO-229WEED-5, MLP-10
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 1995K
代理商： FAN5355MP07X
2008 Fairchild Semiconductor Corporation
3
www.fairchildsemi.com
FAN5355 Rev. 1.0.4
FA
N
5355
—
1A
/
0.8A
,3M
hz.
D
igit
a
lly
Prog
rammabl
e
TinyB
u
ck
TM
Regulator
Pin Configuration
C1
B1
A1
A2
C3
B3
A3
C2
D1
D3
D2
B2
Top View
C1
B1
A1
C3
B3
A3
A2
C2
D1
D3
D2
B2
Bottom View
PAD
AGND
7
8
9
10 SW
PGND
AGND
EN
VOUT
4
3
2
1
PVIN
AVIN
SDA
SCL
VSEL
6
5
Top View
Figure 2. WLCSP- 12, 2.23x1.46mm
Figure 3. MLP10, 3x3mm
Pin Definitions
Pin #
WLCSP
MLP
Name
Description
A1, B1
9
PGND
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The
connection from this pin to the bottom of CIN should be as short as possible.
A2
10
SW
Switching Node. Connect to output inductor.
A3
1
PVIN
Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as
short as possible.
B2
N/A
SYNC
Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin.
In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the
specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock.
B3
2
AVIN
Analog Input Voltage. Connect to input power source as close as possible to the input bypass
capacitor.
C1
8, PAD
AGND
Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect
to this pin.
C2
7
EN
Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This
pin should not be left floating.
C3
3
SDA
SDA. I
2C interface serial data.
D1
6
VOUT
Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit
and does not carry DC current.
D2
5
VSEL
Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior
can be overridden through I
2C register settings. This pin should not be left floating.
D3
4
SCL
SCL. I
2C interface serial clock.
Note:
7.
All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN.
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