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參數(shù)資料
| 型號(hào)： | FM3808 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 4Kb FRAM Serial 3V Memory |
| 中文描述： | 4Kb的鐵電串行3V的記憶 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 191K |
| 代理商： | FM3808 |
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FM3808
Rev 1.1
May 2003
Page 21 of 28
Read Cycle
AC Parameters
(T
A
= -40
°
C to + 85
°
C, V
DD
= 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
t
CE
Chip Enable Access Time ( to data valid)
t
CA
Chip Enable Active Time
t
RC
Read Cycle Time
t
PC
Precharge Time
t
AS
Address Setup Time
t
AH
Address Hold Time
t
OE
Output Enable Access Time
t
HZ
Chip Enable to Output High-Z
t
OHZ
Output Enable to Output High-Z
Write Cycle
AC Parameters
(T
A
= -40
°
C to + 85
°
C, V
DD
= 4.5V to 5.5V unless otherwise specified)
Symbol
Parameter
t
CA
Chip Enable Active Time
t
CW
Chip Enable to Write High
t
WC
Write Cycle Time
t
PC
Precharge Time
t
AS
Address Setup Time
t
AH
Address Hold Time
t
WP
Write Enable Pulse Width
t
DS
Data Setup
t
DH
Data Hold
t
WZ
Write Enable Low to Output High Z
t
WX
Write Enable High to Output Driven
t
HZ
Chip Enable to Output High-Z
t
WS
Write Setup
t
WH
Write Hold
Notes
1
This parameter is periodically sampled and not 100% tested.
2
The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing
specification associated with this relationship.
Power Cycle Timing
(T
A
= -40
°
C to + 85
°
C)
Symbol
Parameter
t
INT
INT signal active after V
TP
t
PD
Last Access Complete to V
LO
t
RI
VLO to inputs recognized on power-up
t
R
Rise time of V
DD
from V
BG
to V
LO
t
F
Fall time of V
DD
from V
LO
to V
BG
Notes
1
This parameter is periodically sampled and not 100% tested.
2
If power monitor is programmed to generate INT.
3
Access is blocked at V
LO
. The last access should be complete prior to reaching V
LO
. The early warning power fail interrupt
may be useful in accomplishing this.
4
Failing to satisfy t
RI
may result in the first access being ignored. Failure to raise /CE to a logic high prior to V
DD
>V
LO
may
result in improper operation.
5
Slew rate for proper transition between the locked-out condition and normal operation.
Min
70
130
60
0
10
Max
70
2,000
10
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
Min
70
70
130
60
0
10
30
30
5
10
0
0
Max
2,000
15
15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
2
2
Min
0
1
100
100
Max
100
Units
ns
ns
μ
s
μ
s
μ
s
Notes
1,2
1,3
1,4
1,5
1,5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FM3808-70-T | 4Kb FRAM Serial 3V Memory |
| FM3808DK | 4Kb FRAM Serial 3V Memory |
| FMA10A | General Purpose(Dual Digital Transistor)(通用(雙數(shù)字晶體管)) |
| FMA11A | Emitter Common (Dual Digital Transistors)(公共發(fā)射級(jí)(雙數(shù)字晶體管)) |
| FMA1 | General purpose (dual digital transistors) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FM3808_06 | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808-70-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808DK | 制造商:RAMTRON 制造商全稱:RAMTRON 功能描述:256Kb Bytewide FRAM w/ Real-Time Clock |
| FM3808-S | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
| FM3808-SG | 制造商:Ramtron International Corporation 功能描述:FRAM RTC 256K SMD 3808 TSOP32 |
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