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| 型號(hào)： | FR65E |
| 廠商： | Fujitsu Limited |
| 英文描述： | 32-Bit Microcontroller |
| 中文描述： | 32位微控制器 |
| 文件頁(yè)數(shù)： | 15/87頁(yè) |
| 文件大?。?/td> | 369K |
| 代理商： | FR65E |
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MB91307B
15
Hardware standby at power-on startup
If a power-on startup is followed immediately by a hardware standby request, the reset initialization of settings
(INIT) from the INIT pin has priority. However in case of transition from the reset initialization (INIT) to hardware
standby, the oscillator stabilization wait period is initialized to maximum duration, and after release of the hardware
standby request the maximum setting is applied to the oscillator stabilization wait period.
Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
Remarks for the external clock operation
When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0
must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops
when “H” is input in STOP mode. To prevent one output from competing against another, in this case, the stop
mode must not be used.
Refer to the Data Sheet for maximum input frequency.
Built-in DC-DC regulator
This device has a built-in regulator, requiring 3.3 V input to the V
cc
pin and a bypass capacitor of approximately
0.1
μ
F connected to the C pin for the regulator.
Note that the A/D converter requires a separate 3.3 V power supply.
MB91307B
X0
X1
Using external clock (normal)
Note : Stop mode (oscillation stop mode) cannot be used.
3.3 V
0.1
μ
F
C
V
CC
AV
CC
AVRH
AV
SS
/AVRL
V
SS
GND
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