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參數(shù)資料
| 型號： | FS612509-02 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1:9 ZERO DELAY CLOCK BUFFER IC |
| 中文描述： | 1:9零延遲時鐘緩沖器集成電路 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 81K |
| 代理商： | FS612509-02 |
AMERICAN MICROSYSTEMS, INC.
November 2000
This document contains information on a new product. Specifications and information herein are subject to change without notice.
QS9000
11.29.00
FS612509-01/-02
1:9 Zero-Delay Clock Buffer IC
1.0 Features
Generates one bank of five outputs (1Y0 to 1Y4) and
one bank of four outputs (2Y0 to 2Y3) from one ref-
erence clock input (CLK)
Designed to meet the PLL Component Specifications
as noted in the PC133 SDRAM Registered DIMM
Design Specification
External feedback input (FBIN) to synchronize all
clock outputs to the clock input
Operating frequency: 25MHz to 140MHz
Tight tracking skew (spread-spectrum tolerant)
On-chip 25
series damping resistors for driving
point-to-point loads
Separate bank controls:
Signal 1G enables or disables outputs 1Y0 - 1Y4
Signal 2G enables or disables outputs 2Y0 - 2Y3
Available with an auto power-down option that turns
off the PLL and forces all outputs low when the refer-
ence clock stops (
FS612509-02
)
Packaged in a 24-pin TSSOP
Figure 1: Block Diagram
FS612509
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
PLL
FBIN
CLK
1G
FBOUT
GND
AVDD
2Y3
VDD
AGND
2G
2.0 Description
The FS612509 is a low skew, low jitter CMOS zero-delay
phase-lock loop (PLL) clock buffer IC designed for high-
speed motherboard applications, such as those using
133MHz SDRAM.
Nine buffered clock outputs are derived from an onboard
open-loop PLL. The PLL aligns the frequency and phase
of all output clocks to the input clock CLK, including an
FBOUT clock that feeds back to FBIN to close the loop.
One group of five outputs 1Y0 to 1Y4 are enabled and
disabled low by the active-high 1G signal. A second
group of four outputs 2Y0 to 2Y3 are enabled and dis-
abled low by the active-high 2G signal. The PLL may be
bypassed by pulling AVDD to ground.
Figure 2: Pin Configuration
1
2
3
4
5
6
7
8
24
23
22
21
20
19
AGND
VDD
1Y0
AVDD
CLK
9
10
11
12
GND
GND
1Y3
1Y4
VDD
1G
FBOUT
18
17
16
15
14
13
2Y3
GND
GND
2Y2
2Y1
VDD
2G
VDD
FBIN
F
1Y1
1Y2
2Y0
Table 1: Function Table
INPUT
OUTPUT
PLL
AVDD
1G
2G
CLK
1Y0-1Y4
2Y0-2Y3
FBOUT
H
H
H
H
H
L
L
L
L
L
L
L
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
Z
P
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