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參數(shù)資料
| 型號： | FS612509-02 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1:9 ZERO DELAY CLOCK BUFFER IC |
| 中文描述： | 1:9零延遲時鐘緩沖器集成電路 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 81K |
| 代理商： | FS612509-02 |
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
QS9000
3
FS612509-01/-02
1:9 Zero-Delay Clock Buffer IC
3.0 Device Operation
The FS612509 is a zero-delay buffer intended for use on
buffered PC133 SDRAM DIMMs.
The FS612509 precisely aligns the frequency and phase
of the output clocks to the input CLK by use of an on-chip
phase-lock loop (PLL). The PLL generates up to 9 low-
skew, low-jitter copies of the CLK, with the outputs ad-
justed for 50% duty cycle.
The FBOUT clock must be hardwired to the FBIN pin to
complete the loop. The PLL actively adjusts the output
clocks so that there is no phase error between the refer-
ence clock (CLK) and the feedback clock (FBIN).
Since the device uses a PLL to lock the output clocks to
the input clock, there is a power-up stabilization time that
is required for the PLL to achieve phase lock.
Note that all inputs and outputs use LVCMOS signal lev-
els.
3.1
When the AVDD pin is pulled low, the reference clock
signal bypasses the PLL and is brought directly through
to the outputs. The PLL is powered down, and device
acts a fanout buffer.
Note that if AVDD is re-established, the PLL requires a
power-up and stabilization time to lock to the input clock.
PLL Bypass
3.2
The FS612509-02 version provides an auto power-down
feature that shuts off the PLL, drives all outputs low, and
places the device into a low current state if the reference
clock stops. The power-down circuit is level sensitive,
and detects either a DC high or low on the CLK input.
Power-Down
3.3
Two banks of clock outputs are available on this device.
Each bank is independently enabled or disabled by the
1G or 2G enable signals.
The first bank consists of five outputs 1Y0 to 1Y4, and
the clocks are enabled or disabled by the 1G signal. A
Bank Output Enable/Disable
logic-high on 1G enables the Bank 1 outputs to swing in
phase with the reference clock CLK. A logic-low on 1G
forces the Bank 1 to a logic-low state.
A second bank of four clock outputs consists of 2Y0 to
2Y3, and the clocks are enabled or disabled by the 2G
signal. A logic-high on 2G enables the Bank 2 outputs to
swing in phase with the reference clock CLK. A logic-low
on 2G forces the Bank 2 to a logic-low state.
The function table Table 1 shows the effect of the 1G and
2G enable signals on the clock outputs.
4.0 Tracking Skew
PLL-based buffer ICs may be required to follow a spread-
spectrum modulated reference clock for frequencies
greater than 66MHz. Spread spectrum modulation limits
peak EMI emissions by intentionally introducing jitter onto
a clock signal, effectively spreading the peak energy over
a range of frequencies.
A downstream PLL, contained in a clock buffer IC such
as this one, must carefully track the modulated input ref-
erence clock. A measure of how closely the downstream
PLL follows the modulated clock is called the tracking
skew. To ensure a tight tracking skew, the loop band-
width of a downstream PLL is increased and the loop
phase angle is reduced over that of typical PLL-based
clock generators.
The type of modulation profile used impacts tracking
skew. The maximum frequency change occurs at the
profile limits where the modulation changes the slew rate
polarity. To track the sudden reversal in clock frequency,
the downstream PLL must have a large loop bandwidth.
The ability of the downstream PLL to catch up to the
modulating clock is determined by the loop transfer func-
tion phase angle.
The spread-spectrum reference clock should be either a
triangle-wave or a non-linear modulation profile, with a
modulation frequency of 50kHz or less.
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