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參數(shù)資料
| 型號： | FS612509-02 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1:9 ZERO DELAY CLOCK BUFFER IC |
| 中文描述： | 1:9零延遲時鐘緩沖器集成電路 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 81K |
| 代理商： | FS612509-02 |
AMERICAN MICROSYSTEMS, INC.
November 2000
ISO9001
QS9000
2
FS612509-01/-02
1:9 Zero-Delay Clock Buffer IC
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
11
14
3
4
5
8
9
21
20
DI
DI
DO
DO
DO
DO
DO
DO
DO
1G
2G
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
Output enable stops Bank 1 clocks (1Y0 – 1Y4) in a low state when this pin is low
Output enable stops Bank 2 clocks (2Y0 – 2Y3) in a low state when this pin is low
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Clock output
Bank 1
Enabled by 1G
17
16
DO
DO
2Y2
2Y3
Clock output
Clock output
Power Supply / Test mode enable. This pin provides the power supply to the internal PLL. When the
pin is pulled low, the PLL is bypassed and the output clocks directly follow the input clock
PLL supply ground
Reference clock input (
Note: -02 version has a pull-down on this pin
)
Bank 2
Enabled by 2G
23
P
AVDD
1
P
DI
AGND
CLK
24
13
12
DI
DO
P
P
FBIN
FBOUT
GND
VDD
Feedback clock input, connected to FBOUT to complete the loop
Feedback output clock
Ground for all clock outputs
Power supply for all clock outputs
6, 7, 18, 19
2, 10, 15, 22
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