- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370260 > FW803-09-DB PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device PDF資料下載
參數(shù)資料
| 型號(hào)： | FW803-09-DB |
| 英文描述： | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| 中文描述： | PHY的IEEE 1394A端口三線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 395K |
| 代理商： | FW803-09-DB |
Data Sheet, Rev. 3
June 2001
FW803 PHY
IEEE
1394A
Three-Cable Transceiver/Arbiter Device
Lucent Technologies Inc.
3
Description
(continued)
Each cable port incorporates two differential line trans-
ceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connec-
tion status, for initialization and arbitration, and for
packet reception and transmission. The PHY is
designed to interface with a link-layer controller (LLC).
The PHY requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which
generates the required 400 MHz reference signal. The
400 MHz reference signal is internally divided to
provide the 49.152 MHz, 98.304 MHz, and
196.608 MHz clock signals that control transmission of
the outbound encoded strobe and data information.
The 49.152 MHz clock signal is also supplied to the
associated LLC for synchronization of the two chips
and is used for resynchronization of the received data.
The powerdown function, when enabled by the PD
signal high, stops operation of the PLL and disables all
circuitry except the cable-not-active signal circuitry.
The PHY supports an isolation barrier between itself
and its LLC. When /ISO is tied high, the link interface
outputs behave normally. When /ISO is tied low,
internal differentiating logic is enabled, and the outputs
become short pulses, which can be coupled through a
capacitor or transformer as described in the
IEEE
1394-1995 Annex J. To operate with bus-keeper
isolation, the /ISO pin of the FW803 must be tied high.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in
synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and
transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or
393.216 Mbits/s as the outbound data-strobe
information stream. During transmission, the encoded
data information is transmitted differentially on the TPA
and TPB cable pair(s).
During packet reception, the TPA and TPB
transmitters of the receiving cable port are disabled,
and the receivers for that port are enabled. The
encoded data information is received on the TPA and
TPB cable pair. The received data-strobe information
is decoded to recover the receive clock signal and the
serial data bits. The serial data bits are split into two,
four, or eight parallel streams, resynchronized to the
local system clock, and sent to the associated LLC.
The received data is also transmitted (repeated) out of
the other active (connected) cable ports.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states
during initialization and arbitration. The outputs of
these comparators are used by the internal logic to
determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage.
The value of this common-mode voltage is used during
arbitration to set the speed of the next packet
transmission. In addition, the TPB channel monitors
the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias
voltage. This monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. This bias voltage, when seen
through a cable by a remote receiver, indicates the
presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33
μ
F.
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry, the receiver circuitry, and the TPBIAS output
are also disabled when the port is disabled,
suspended, or disconnected.
The line drivers in the PHY operate in a high-
impedance current mode and are designed to work
with external 112
line-termination resistor networks.
One network is provided at each end of each twisted-
pair cable. Each network is composed of a pair of
series-connected 56
resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 k
and 220 pF, respectively.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW803 | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| FW804-09-DB | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| FW804 | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| FW80960RP-33 | I/O Controller |
| FW82439HX | System Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW80321M400 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80321 I/O Processor |
| FW80321M400SL6R2 | 功能描述:IC I/O PROCESSOR CMOS 544BGA PKG RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點(diǎn):- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應(yīng)商設(shè)備封裝:516-PBGAPGE（27x27） 包裝:托盤 |
| FW80321M600SL6R3 | 功能描述:IC MPU 32-BIT PCI XSCALE 544BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| FW804 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| FW804-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。