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參數(shù)資料
| 型號： | FW803-09-DB |
| 英文描述： | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
| 中文描述： | PHY的IEEE 1394A端口三線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 395K |
| 代理商： | FW803-09-DB |
8
Agere Systems Inc.
Data Sheet, Rev. 3
June 2001
Three-Cable Transceiver/Arbiter Device
FW803 PHY
IEEE
1394A
Signal Information
(continued)
Table 1. Signal Descriptions
(continued)
Pin
Signal
*
Type
Name/Description
16
LPS
I
Link Power Status.
LPS is connected to either the V
DD
supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2
μ
s and less than 25
μ
s, interface is reset. If LPS is inactive for
greater than 25
μ
s, the PHY will disable the PHY/Link interface to save
power. FW803 continues its repeater function.
Link Request.
LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
Power-Class Indicators.
On hardware reset, these inputs set the default
value of the power class indicated during self-ID. These bits can be
programmed by tying the signals to V
DD
(high) or to ground (low).
1
LREQ
I
20
21
22
19
PC0
PC1
PC2
PD
I
I
Powerdown.
When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal.
Power for PLL Circuit.
PLLV
DD
supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-impedance ground
plane.
Current Setting Resistor.
An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
±
1% should be used to meet the
IEEE
1394-1995 standard requirements for output voltage limits.
57
PLLV
DD
—
58
PLLV
SS
—
54
R0
I
55
R1
61
/RESET
I
Reset (Active-Low).
When /RESET is asserted low (active), the FW803
is reset. An internal pull-up resistor, which is connected to VDD, is
provided, so only an external delay capacitor is required to ensure that the
capacitor is discharged when PHY power is removed. This input is a stan-
dard logic buffer and can also be driven by an open-drain logic output
buffer.
Test Mode Control.
SE is used during the manufacturing test and should
be tied to V
SS
.
Test Mode Control.
SM is used during the manufacturing test and should
be tied to V
SS
.
System Clock.
SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
Analog I/O
Portn, Port Cable Pair A.
TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
28
SE
I
29
SM
I
63
SYSCLK
O
36
TPA0+
41
TPA1+
47
TPA2+
35
TPA0
Analog I/O
Portn, Port Cable Pair A.
TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
40
TPA1
46
TPA2
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
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