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參數資料
| 型號： | FX980L6 |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 29/86頁 |
| 文件大?。?/td> | 821K |
| 代理商： | FX980L6 |
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TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
35
D/980/3
RamDacCtrl
Title:
RamDac Control register
Address:
$0x0C
Function:
RW
Description:
This register controls the operation of DAC 1, together with the operation of the memory
(DacSram) which can be used to drive the digital input of DAC 1.
Bit
Name
Active State
Function
7:6
RW
Reserved. These bits should be set Low. Undefined on
read.
5:3
RamDacRate
High
RW
These three bits set the rate at which the RamDac
memory’s DAC access address pointer changes. The three
bit value (RamDacRate) causes a change rate of
(36 x
2
RamDacRate) kHz. See table below.
2
RamDacInc
High
RW
This bit activates the RamDac memory scan operation.
Setting it active will cause the memory address to
increment up to the top (highest) location, conversely
setting the bit inactive will cause the memory address to
decrement down to the bottom location. If the bit is
changed while the memory is being scanned, the current
scan will complete before the new state of the RamDacInc
bit takes effect.
1
AutoCycle
High
RW
This bit is only valid if the RamDacActive bit is active.
When set active, the Auxiliary SRAM memory will be
continually scanned at the rate set by the RamDacRate
bits. This enables a symmetrical periodic waveform to be
driven out on the AUXDAC1 pin. The Auxiliary SRAM
address cycles from the bottom location up to the top
location, and back down to the bottom again.
0
RamDacActive
High
RW
DAC 1 input mode bit. When inactive, the AuxDacData
registers (offsets 0 and 1) are used as the source for
conversion. If this bit is active, the DAC is driven from the
output of the RamDac memory.
Ram Dac Rate Select Table
RamDacCtrl[5:3]
Dac Update Frequency
(kHz)
0 0 0
36
0 0 1
72
0 1 0
144
0 1 1
288
1 0 0
576
1 0 1
1152
1 1 0
2304
1 1 1
4608
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