參數(shù)資料
型號： FX980L6
廠商： CML MICROSYSTEMS PLC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 60/86頁
文件大?。?/td> 821K
代理商： FX980L6
TETRA Baseband Processor
FX980
1997 Consumer Microcircuits Limited
63
D/980/3
RxIQGainMult
Title:
Receive I and Q channel Gain Multiplier register
Address:
$0x30, $0x31, $0x34 and $0x35 (4 locations)
Function:
RW
Description:
A 2s-complement multiplication is performed on the magnitude of the Rx Data path signal and
the result is then re-normalised to the system’s dynamic range: thus the function may be
considered as a digital attenuator. This multiplication is applied to the Rx signal after the ADC
decimation filter, but before offset adjustment and the 63-tap and 49-tap FIR filters. This register
sets the multiplier, the result being given by the formula:
D
G
2
out
in
val
15
=
Where:
Din
Dout
G
val
is the signal input,
is the signal output,
is the value in the register.
Bit
Name
Active State
Function
Address $0x30
7:0
RxIGainLSB
Data RW
Least significant 8 bits of the RxIGain register (G
val).
Address $0x31
7:3
RW
Reserved. Set these bits Low. Undefined on read.
2:0
RxIGainMSB
Data RW
Most significant 3 bits of the RxIGain register (G
val).
Address $0x34
7:0
RxQGainLSB
Data RW
Least significant 8 bits of the RxQGain register (G
val).
Address $0x35
7:3
RW
Reserved. Set these bits Low. Undefined on read.
2:0
RxQGainMSB
Data RW
Most significant 3 bits of the RxQGain register (G
val).
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