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參數(shù)資料
| 型號： | GBP32 |
| 英文描述： | The GigaBridge Switched-PCI Controller|GBP Reset Design Note |
| 中文描述： | 在GigaBridge開關(guān)PCI控制器|英鎊復(fù)位設(shè)計筆記 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 275K |
| 代理商： | GBP32 |
4. SIGNAL DEFINITION – SAMPLE CIRCUITS
This section provides the polarities and descriptions of various signals needed.
Table 3. Signal Definition
Name
Direction
(With respect to
logic circuit)
Input
Description
Clk
Any clock frequency can be used.
Prst_N
Input
Active low PCI Bus reset.
ResetOut_N
Input
Active low reset signal from power supply switch, which keeps
GBP in reset state until Power is good.
Generates the IamClusMgr signal for the GBP.
Active high for the Primary node in Hardware Auto-
configuration mode. Active low in all other modes.
Active low regenerated power on reset to GBP.
ClusMgrIn
Input
Por_N
Output
Lrsti_N
Output
Active low regenerated PCI Bus reset which goes to GBP
ClusMgr
Output
Regenerated IamClusMgr information to GBP.
Active high signal.
GBP/Reset Design Note v1.0
2002 PLX Technology, Inc. All rights reserved.
4
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