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參數(shù)資料
| 型號(hào)： | GBP32 |
| 英文描述： | The GigaBridge Switched-PCI Controller|GBP Reset Design Note |
| 中文描述： | 在GigaBridge開(kāi)關(guān)PCI控制器|英鎊復(fù)位設(shè)計(jì)筆記 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | GBP32 |
5. PRIMARY NODE OPERATION
The basic operation of the GBP reset for the Primary Node:
Upon de-assertion of Por_N, the GBP samples the presence of PCLK. If the GBP doesn’t
sample PCLK within Tpp, it starts generating its own PCLK. If the host computer does not
generate PLCK within Tpp, the GBP begins generating PCLK. If the host computer then starts
to generate PCLK, there will be contention on the PCLK line.
After Por_N de-assertion, GBP samples de-assertion of Lrsti_N to determine the state of unique
CSR registers, such as IamDomMgr and AssertReq64AtRst. The GBP configuration depends
on these registers to determine whether the node is a primary node or a secondary node, or to
determine if it must operate in 32-bit or 64-bit mode.
Three different sample circuits for Primary Node operation are shown in Table 4. Sample circuit A is the
simplest, but only supports Hardware Autoconfiguration up to 2 nodes. Sample circuits B and C support
larger systems using Hardware Autoconfiguration. All three circuits support Serial EEPROM
configuration.
Table 4. Sample Circuits
Case
Hardware
Autoconfiguration
Serial EEPROM
Configuration
Figure
Notes
A
Supports 2-node
system only.
Supports systems
with any number
of nodes.
5
Simplest and cheapest circuit
to implement.
Recommended for serial
EEPROM configuration.
B
Supports systems
with greater than 2-
nodes.
Supports systems
with any number
of nodes.
6
Implemented using delay lines.
The logic circuit shown has
been verified by behavioral
simulation only.
A physical implementation has
not been verified.
Any convenient clock can be
used for “Clk”.
C
Supports systems
with greater than 2-
nodes.
Supports systems
with any number
of nodes.
7
Implemented using delay
counters.
The logic circuit shown has
been tested by Verilog code
implementation in a CPLD.
This code is provided in
Section 7.
Sample circuit requires 1MHz
“Clk”.
GBP/Reset Design Note v1.0
2002 PLX Technology, Inc. All rights reserved.
5
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