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參數(shù)資料
| 型號(hào)： | GBP32 |
| 英文描述： | The GigaBridge Switched-PCI Controller|GBP Reset Design Note |
| 中文描述： | 在GigaBridge開關(guān)PCI控制器|英鎊復(fù)位設(shè)計(jì)筆記 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 275K |
| 代理商： | GBP32 |
6. SECONDARY NODE OPERATION
If the de-assertion of the reset signal (ResetOut_N) from the power supply can be provided to facilitate
the de-assertion of Por_N to the secondary GBP device, the secondary node is not required to have the
reset logic implemented.
After Por_N de-assertion the GBP will use MCLK (local oscillator) to generate the PCI bus clock
in the absence of an external PCI clock.
After Por_N de-assertion, GBP samples de-assertion of Lrsti_N to determine the state of unique
CSR registers, such as IamDomMgr and AssertReq64AtRst. The GBP configuration depends
on these registers to determine whether the node is a primary node or a secondary node, or to
determine if it must operate in 32-bit or 64-bit mode.
All of the secondary GBP nodes must come out of reset before the primary GBP node comes
out of reset in order for the GBP system to operate properly
No circuitry is required for the secondary nodes, however the following connections should be
made:
o
Tie the ResetOut_N line directly to the PwrOn# pin of the secondary GBP devices.
o
Tie the IamClusMgr pin on the secondary GBP devices to 0.
o
Tie the RST# pin on the secondary GBP devices to 1.
These connections can be used with any of the three different sample circuits for Primary Nodes, as
shown in Table 4.
GBP/Reset Design Note v1.0
2002 PLX Technology, Inc. All rights reserved.
9
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