
***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
23
C5115-DAT-01H
HS(system)
active
active
capture
HS(internal)
capture
capture
programmable
delay
input block actually
captures across HSYNC
Figure 15.
HSYNC Delay
Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with
respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but with
different paths to the gm5115/25 (HSYNC is often regenerated from a PLL). As a result,
VSYNC may be seen earlier or later. Because VSYNC is used to reset the line counter and
HSYNC is used to increment it, any difference in the relative position of HSYNC and VSYNC is
seen on-screen as vertical jitter. By delaying the HSYNC a small amount, it can be ensured that
VSYNC always resets the line counter prior to it being incremented by the “first” HSYNC.
delayed HS placed safely within blanking
active data crosses HS boundary
Data
HS (system)
Internal Delayed HS
Figure 16.
Active Data Crosses HSYNC Boundary
4.6.2 Horizontal and Vertical Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC
signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal
measurements are performed on only a single line per frame (or field). The line used is
programmable. It is able to measure the vertical period and VSYNC pulse width in terms of
rising edges of HSYNC.
Once enabled, measurement begins on the rising VSYNC and is completed on the following
rising VSYNC. Measurements are made on every field / frame until disabled.
4.6.3 Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and then
alert both the system and the on-chip microcontroller. The microcontroller sets a measurement
difference threshold separately for horizontal and vertical timing. If the current field / frame