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10
GP2000 – GPS CHIPSET DESIGNER’S GUIDE
GPS ARCHITECT HARDWARE AND SOFTWARE OVERVIEW
SYSTEM OVERVIEW
The GPS Architect is a development system intended for
Global Positioning System (GPS) receiver design where a GPS
receiver function needs to be embedded within OEM products
at low cost.
GPS Architect operates as a 12-channel ‘All-in-View’ GPS
receiver. The product is a stand-alone receiver, with all the
processing of GPS signals done on a single PCB, with a PC
used as a software development tool in conjunction with monitor
software (WINMON) which allows the GPS function of the GPS
Architect to be monitored and controlled.
This section provides an overview of the component parts of
GPS Architect.
GPS Architect comprises a single printed circuit board of
overall size 200mm3170mm, which fits into a thin-profile
equipment case. The board contains the GP2000 chipset, which
includes:
GP2010 RF front-end (sister product of the GP2015)
DW9255 3542MHz SAW with 2MHz bandwidth
GP2021 12-channel correlator
ARM 60-B 32-bit RISC microprocessor
Fig. 11 is a block diagram of the circuit used for GPS Archi-
tect and the component layout is shown in Fig. 12.
The GPS Architect operates in conjunction with a PC which
uses a compiler for the ARM 60-B: the ARM Toolkit. Source
code for the GPS Architect can be written in the C programming
language, and compiled on the PC. The compiled binary image
file produced can be passed along an RS232 connection from
the PC to the DEBUG RS232 port on the GPS Architect, and
stored in fast SRAM memory, with the help of UMON software
which is executed from EPROM. The code execution can be
controlled from the PC.
The function of the ARM Toolkit with the GPS Architect is
explained in the GPS Architect Data Sheet (DS4605).
One GP2021 UART port is used by the PC-based monitor
for receiver control and data display. The second UART port is
available for DGPS corrections.
Both the ARM Toolkit and the receiver monitor programs are
Windows based.
GP2000 CHIPSET
GP2010 RF FRONT END
DW9255 SAW FILTER
ARM 60-B RISC
P
GP2021 CORRELATOR
10MHz
TEMPERATURE
COMPENSATED
CRYSTAL
OSCILLATOR
32MHz
REAL TIME
CLOCK
CRYSTAL
2
3RS232
I/O DRIVERS
RANDOM
ACCESS
MEMORY
4MBIT
READ
ONLY
MEMORY
4MBIT
LOGIC
ANAL
YSER
ACCESS
PORTS
13UART
AND
RS232
I/O DRIVER
MEMORY CONTROL BUS
ADDRESS BUS
DATA BUS
TX/RX PORT A
TX/RX PORT B
DEBUG PORT
LINK TO PC SERIAL PORTS
RF FILTER
GPS
ACTIVE
ANTENNA
POWER
CONDITIONING
1
5V ANALOG AND
DIGITAL SUPPLIES
8V TO 13V DC INPUT
FROM AC ADAPTER
(SUPPLIED)
Fig. 11 GPS Architect block diagram