參數(shù)資料
型號: GP2000
廠商: Mitel Networks Corporation
英文描述: ()
中文描述: ()
文件頁數(shù): 24/25頁
文件大?。?/td> 256K
代理商: GP2000
8
GP2000 – GPS CHIPSET DESIGNER’S GUIDE
Tracking Module
The GP2021 has 12 identical tracking module blocks, one
for each channel. Each block (shown in Fig. 9) contains all the
components necessary for acquiring and tracking the received
signal (code generator, code DCO, carrier DCO, mixers and
accumulators). Each block also contains other functional blocks
which are used to produce part of the measurement data set
(epoch counter and carrier cycle counter).
Code Generator
The Code Generator can generate the following pseudo-ran-
dom codes:
(i) GPS satellite C/A codes for PRNs 1 to 32.
(ii) Pseudolite C/A codes for PRNs 33 to 37.
(iii) INMARSAT GIC codes for PRNs 201 to 211
The generated code is supplied to the Prompt and Track
arms. The Track arm code can be configured to 4 different modes
with respect to the Prompt arm code phase:
(i) Early: permanently 1/2 chip early (advanced).
(ii) Late: permanently 1/2 chip late (retarded).
(iii) Early-Minus-Late: signed difference of Early and Late.
(iv) Dithered: alternates between Early and Late every 20ms.
Code DCO
The Code DCO clocks the code generator at nominally twice
the C/A code rate (2046MHz). This rate is required to produce
the Track arm codes phased by 1/2 chip with respect to the
Prompt arm code.
A 26-bit long counter clocked at 40/7MHz (for a 40MHz mas-
ter clock) provides a resolution of approximately 85149mHz
(42575mHz at the C/A code rate).
It is programmed via the following registers:
CHx_CODE_DCO_INCR_HIGH: DCO bits 24 to16 and
CHx_CODE_DCO_INCR_LOW: DCO bits 15 to 0.
A control word of 016EA4A9hex gives a C/A code rate of
nominally 1023 MHz.
Code Phase Counters
This block contains counters for determining the code phase
of the Prompt arm. At each TIC the counters are sampled and
the data is stored in the following registers:
CHx_CODE_PHASE: gives the number of 1/2 chips of code
phase in the range 0 to 2046.
CHx_CODE_DCO_PHASE: gives the fractional code phase
below 1/2 a chip. It takes values from 0 to 1023 with a resolution
of 1/2048 (approximately 05 ns or 015 m) of a chip.
Epoch Counters
This block contains counters for determining the com-
plete number of code cycles (epochs) on the Prompt arm.
At each TIC, the counters are sampled and the data is
stored in the CHx_EPOCH_COUNT register, which con-
tains the number of 1 ms (in the range 0 to 19) and 20ms
(in the range 0 to 49) epochs. Hence, the Code Phase
registers can be combined with the Epoch Count register
to give a code time between 0 and 1 second at a resolu-
tion of approximately 05ns.
Carrier DCO
The carrier DCOs are used to mix the input signal to baseband
prior to correlation with the locally generated codes.
A 27-bit long counter clocked at 40/7MHz (for a 40MHz mas-
ter clock) provides a resolution of approximately 42575mHz.
The carrier DCOs generate 4 level, 8 phase sinusoids with
the sequence over 1 cycle as shown in Fig. 10.
When the input signal is already in complex (I, Q) form the
quadrature DCO can be configured to generate an in-phase
carrier.
It is programmed via the following two registers:
(i) CHx_CARRIER_DCO_INCR_HIGH: DCO bits 25 to 16.
(ii) CHx_ CARRIER_DCO_INCR_LOW: DCO bits 15 to 0.
When used with a GP2015 a control word 01F7B1B9 hex
gives a carrier DCO frequency rate of approximately
1405397 MHz.
Fig. 9 GP2021 tracking module architecture
DATA
BUS
Q_TRACK
ACCUMULATOR
Q_PROMPT
ACCUMULATOR
C/A CODE
GENERATOR
EPOCH
COUNTERS
I_PROMPT
ACCUMULATOR
I_TRACK
ACCUMULATOR
CODE DCO
CODE PHASE
COUNTERS
CODE SLEW
TRACK
ARM
PROMPT
ARM
CARRIER
DCO
CARRIER CYCLE
COUNTER
IN PHASE OR
QUADRATURE
IN PHASE
SOURCE
SELECTOR
SIGN0 & MAG0
SIGN1 & MAG1
SELECT SOURCE
AND MODE
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