參數(shù)資料
型號(hào): GS8161E18GT-166I
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 1M X 18 CACHE SRAM, 7 ns, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 2/36頁(yè)
文件大?。?/td> 935K
代理商: GS8161E18GT-166I
GS8161E18(T/D)/GS816132(D)/GS816136(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.14 3/2005
10/36
1999, GSI Technology
Note:
Thereis a pull-up deviceonthe FT pin and a pull-down device on the ZZ pin, so input pin can be unconnected and the chip will operate in the
default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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