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參數(shù)資料
| 型號： | GS8161Z36AGT-275I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 5.25 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 40/40頁 |
| 文件大?。?/td> | 1178K |
| 代理商： | GS8161Z36AGT-275I |
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Rev: 1.02a 9/2002
1/32
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
GS8161Z18/36AT-300/275/250/225/200
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
300 MHz–200 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V or 2.5 V +10%/–10% core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2M, 4M, and 8M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard 100-lead TQFP package
Functional Description
The GS8161Z18/36AT is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8161Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-300 -275 -250 -225 -200 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.2
3.3
2.4
3.6
2.5
4.0
2.7
4.4
3.0
5.0
ns
1.8 V
Curr (x18)
Curr (x36)
320
375
300
345
275
320
250
295
230
265
mA
2.5 V
Curr (x18)
Curr (x36)
320
370
300
340
275
315
250
285
225
260
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.0
5.25
5.5
6.0
6.5
ns
1.8 V
Curr (x18)
Curr (x36)
220
265
215
260
210
245
200
235
190
225
mA
2.5 V
Curr (x18)
Curr (x36)
220
265
215
260
210
245
200
235
190
225
mA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161Z36B | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36BD | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z36BD-150 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays |
| GS8161Z36BD-150I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 18MBIT 512KX36 7.5NS/3.8NS 165FBGA - Trays |
| GS8161Z36BD-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 18MBIT 512KX36 7.5NS/3.8NS 165FPBGA - Trays |
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