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參數(shù)資料
| 型號： | GS82032AT-4I |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 64K X 32 CACHE SRAM, 10 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 750K |
| 代理商： | GS82032AT-4I |
GS82032AT-180/166/150/133/100/66/4/5/6
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.13 1/2009
8/22
2000, GSI Technology
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
WR
R
WR
X
Simple
Synchronous
Operation
Simple
Burst
Synchronou
sOperation
CR
R
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control
inputs, and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
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| GS82032AT5 | 制造商:GSI Technology 功能描述: |
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