參數(shù)資料
型號(hào)： GS880Z18CT-250IVT
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 512K X 18 ZBT SRAM, QFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 1/24頁(yè)
文件大?。?/td> 804K
代理商： GS880Z18CT-250IVT
GS880Z18/32/36CT-xxxV
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.02a 12/2010
1/24
2010, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM, NoBL and
ZBT SRAMs
1.8 V or 2.5 V +10%/–10% core power supply
1.8 V or 2.5 V I/O supply
User-configurable Pipeline and Flow Through mode
LBO pin for Linear or Interleave Burst mode
Pin compatible with 2M, 4M, and 18M devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ Pin for automatic power-down
JEDEC-standard 100-lead TQFP package
RoHS-compliant 100-lead TQFP package available
Functional Description
The GS880Z18/32/36CT-xxxV is a 9Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS880Z18/32/36CT-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS880Z18/32/36CT-xxxV is implemented with GSI's
high performance CMOS technology and is available in a
JEDEC-standard 100-pin TQFP package.
Parameter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
3.0
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
175
200
150
165
125
145
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
135
155
125
140
113
125
mA
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