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參數(shù)資料
| 型號： | GS8324Z36B-150IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, BGA-119 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 1157K |
| 代理商： | GS8324Z36B-150IT |
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Rev: 1.00 10/2001
20/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Note:
There are pull-up devices on the ZQ, SCD DP, and FT pins and a pull-down devices on the PE and ZZ pins, so those input pins can
be unconnected and the chip will operate in the default states as specified in the above tables.
Enable/Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits
generated and read into the ByteSafe parity circuits.
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Parity Enable
PE
L or NC
Activate 9th I/O’s (x18/36 Mode)
H
Deactivate 9th I/O’s (x16/32 Mode)
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8324Z36GB-250IT | 1M X 36 ZBT SRAM, 6 ns, PBGA119 |
| GS8324Z72GC-133IT | 512K X 72 ZBT SRAM, 10 ns, PBGA209 |
| GS840E18GB-100T | 256K X 18 CACHE SRAM, 12 ns, PBGA119 |
| GS840E18GB-180 | 256K X 18 CACHE SRAM, 8 ns, PBGA119 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS8324Z72C200 | 制造商:G.S.I. 功能描述: |
| GS8342D06BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-550 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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