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參數(shù)資料
| 型號(hào)： | GS8324Z36B-150IT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 1.27 MM PITCH, BGA-119 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 1157K |
| 代理商： | GS8324Z36B-150IT |
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Rev: 1.00 10/2001
34/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Instruction Register
ID Code Register
Boundary Scan Register
0
1
2
0
1
2
31 30 29
0
1
2
n
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8324Z36GB-250IT | 1M X 36 ZBT SRAM, 6 ns, PBGA119 |
| GS8324Z72GC-133IT | 512K X 72 ZBT SRAM, 10 ns, PBGA209 |
| GS840E18GB-100T | 256K X 18 CACHE SRAM, 12 ns, PBGA119 |
| GS840E18GB-180 | 256K X 18 CACHE SRAM, 8 ns, PBGA119 |
| GS8641E18F-200IT | 4M X 18 CACHE SRAM, 7.5 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8324Z36B-200I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 7.5NS/3NS 119FBGA - Trays |
| GS8324Z72C200 | 制造商:G.S.I. 功能描述: |
| GS8342D06BD-350 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-500 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342D06BD-550 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
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