參數(shù)資料
型號(hào)： GS8324Z36GB-250IT
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 1M X 36 ZBT SRAM, 6 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, BGA-119
文件頁(yè)數(shù)： 42/46頁(yè)
文件大?。?/td> 1157K
代理商： GS8324Z36GB-250IT
Rev: 1.00 10/2001
5/46
2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS8324Z18(B/C)/GS8324Z36(B/C)/GS8324Z72(C)
GS8324Z18/36/72 209-Bump BGA Pin Description
Pin Location
Symbol
Type
Description
W6, V6
A0, A1
I
Address field LSBs and Address Counter Preset Inputs.
W7, W5, V9, V8, V7, V5, V4, V3, U8, U6, U4,
A3, A5, A7, B7, A9, U7
An
I
Address Inputs
B5
A19
I
Address Inputs (x36/x18 Versions)
C7
A20
I
Address Inputs (x18 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9
I/O
Data Input and Output pins (x72 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O
Data Input and Output pins (x36 Version)
L11, M11, N11, P11, L10, M10, N10, P10, R10
J1, H1, G1, F1, J2, H2, G2, F2, E2
DQA1–DQA9
DQB1–DQB9
I/O
Data Input and Output pins (x18 Version)
C9, B8
BA, BB
I
Byte Write Enable for DQA, DQB I/Os; active low
B3, C4
BC,BD
I
Byte Write Enable for DQC, DQD I/Os; active low
(x72/x36 Versions)
C8, B9, B4, C3
BE, BF, BG,BH
I
Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
(x72 Version)
B5
NC
—
No Connect (x72 Version)
C7
NC
—
No Connect (x72/x36 Versions)
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,
B4, C3
NC
—
No Connect (x36/x18 Versions)
B3, C4
NC
—
No Connect (x18 Version)
C5, D4, D5, D7, D8, K1, K2, K4, K8, K9, K10,
K11, T4, T5, T7, T8, U3, U5, U9
NC
—
No Connect
K3
CK
I
Clock Input Signal; active high
C6
E1
I
Chip Enable; active low
A8
E3
I
Chip Enable; active low (x72/x36 Versions)
A4
E2
I
Chip Enable; active high (x72/x36 Versions)
D6
G
I
Output Enable; active low
A6
ADV
I
Burst address counter advance enable
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