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參數(shù)資料
| 型號(hào)： | GS840H32A |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 4Mb（128K x 32Bit) Synchronous Burst SRAM(4M位（128K x 32位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 4Mb的（128K的x 32位）同步突發(fā)靜態(tài)存儲(chǔ)器（4分位（128K的× 32位）同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁數(shù)： | 12/31頁 |
| 文件大?。?/td> | 940K |
| 代理商： | GS840H32A |
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Rev: 1.07 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
12/31
1999, Giga Semiconductor, Inc.
Preliminary
GS840H18/32/36AT/B-200/180/166/150/100
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
5
X
X
X
R
R
W
CR
CR
CW
CW
E
1
E
2
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1.
X = Don’t Care, H = High, L = Low.
2.
E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1.
3.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
L
L
X
H
X
H
X
H
X
H
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
H
L
H
H
H
X
H
X
H
X
H
X
L
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
5.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
6.
7.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS840H18A | 4Mb（256K x 18Bit) Synchronous Burst SRAM(4M位（256K x 18位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| GS840H36A | 4Mb（128K x 36Bit) Synchronous Burst SRAM(4M位（128K x 36位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| GS840H32 | 4Mb（128K x 32Bit) Synchronous Burst SRAM(4M位（128K x 32位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| GS840H18 | 4Mb（256K x 18Bit) Synchronous Burst SRAM(4M位（256K x 18位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| GS840H36 | 4Mb（128K x 36Bit) Synchronous Burst SRAM(4M位（128K x 36位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS840H32AB-100 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| GS840H32AB-100I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
| GS840H32AB-150 | 制造商:GSI Technology 功能描述:2.5 OR 3.3V - Trays |
| GS840H32AB-150I | 制造商:GSI Technology 功能描述:2.5 OR 3.3V - Trays |
| GS840H32AB-166 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs |
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