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參數(shù)資料
| 型號(hào)： | GS840H36 |
| 廠(chǎng)商： | GSI TECHNOLOGY |
| 英文描述： | 4Mb（128K x 36Bit) Synchronous Burst SRAM(4M位（128K x 36位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 4Mb的（128K的x 36Bit）同步突發(fā)靜態(tài)存儲(chǔ)器（4分位（128K的× 36位）同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁(yè)數(shù)： | 13/31頁(yè) |
| 文件大?。?/td> | 626K |
| 代理商： | GS840H36 |
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Rev: 2.04 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
13/31
1999, Giga Semiconductor, Inc.
GS840H18/32/36T/B-180/166/150/100
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
S
S
CR
R
CW
CR
CR
Notes:
1.
2.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
The upper portion of the diagram assumes active use of only the Enable (E
1,
E
2,
E
3
) and Write (B
A
, B
B
, B
C
, B
D
, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
3.
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| GS840H36AB-100 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX36 12NS/4.5NS 119FBGA - Trays |
| GS840H36AB-100I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX36 12NS/4.5NS 119FBGA - Trays |
| GS840H36AB-150 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX36 10NS/3.8NS 119FBGA - Trays |
| GS840H36AB-150I | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX36 10NS/3.8NS 119FBGA - Trays |
| GS840H36AB-166 | 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 3.3V 4MBIT 128KX36 8.5NS/3.5NS 119FBGA - Trays |
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