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參數(shù)資料
| 型號： | GS84118B-133 |
| 英文描述： | x18 Synchronous SRAM |
| 中文描述： | x18同步SRAM |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 584K |
| 代理商： | GS84118B-133 |
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Rev: 1.05 7/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
23/30
1999, Giga Semiconductor, Inc.
GS84118T/B-166/150/130/100
Test Mode Description
Functional Description
The GS84118 provides JTAG boundary scan interface using IEEE standard 1149.1 protocol. The Test mode is intended to provide
a mechanism for testing the interconnect between master (processor, controller, etc.), SRAM, other components and the Printed
Circuit Board.
Test Access Port (TAP)
Four pins (as defined in Pin Description Tables) are used to performed JTAG functions. TDI input is used to scan test data serially
into one of three registers (Instruction Register, Boundary Scan Register and Bypass Register). TDO is the output pin to serially
output scan test data. The TDI sends the data into the LSB of the selected register and the MSB of that register feeds the data to
TDO. TMS input pin controls the state transition of 16 state TAP controllers, as specified in IEEE standard 1149.1. Inputs on TDI
and TMS are registered on the rising edge of TCK clock, and the output data on TDO is presented on the falling edge of TCK. The
TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift -DR state.
TAP Controller
Sixteen state controllers are implemented as specified in IEEE standard 1149.1.
The controller enters the Reset state either through
Power up or
Apply logic 1 on TMS input pin on 5 consecutive rising edges.
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
1
1
1
1
Tap Controller State Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS84118B-150 | x18 Synchronous SRAM |
| GS84118B-166 | x18 Synchronous SRAM |
| GS84118T-100 | x18 Synchronous SRAM |
| GS84118T-133 | x18 Synchronous SRAM |
| GS84118T-150 | x18 Synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS84118B-150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Synchronous SRAM |
| GS84118B-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118B-166 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118B-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
| GS84118I-133I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:256K x 18 Sync Cache Tag |
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