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參數(shù)資料

型號(hào)：	GS8644V18GE-150
廠商：	GSI TECHNOLOGY
元件分類：	SRAM
英文描述：	4M X 18 CACHE SRAM, 7.5 ns, PBGA165
封裝：	15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁數(shù)：	14/40頁
文件大?。?/td>	1195K
代理商：	GS8644V18GE-150

Product Preview

GS8644V18(B/E)/GS8644V36(B/E)/GS8644V72(C)

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.03 11/2004

21/40

2003, GSI Technology

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

AC Electrical Characteristics

Parameter

Symbol

-250

-225

-200

-166

-150

-133

Unit

Min

Max

Min

Max

Min

Max

Min

Max Min Max Min Max

Pipeline

Clock Cycle Time

tKC

4.0

—

4.4

—

5.0

—

6.0

—

6.7

—

7.5

—

ns

Clock to Output Valid

(x18/x36)

tKQ

—

2.3

—

2.5

—

2.7

—

2.9

—

3.3

—

3.5

ns

Clock to Output Valid

(x72)

tKQ

—

2.6

—

2.7

—

2.8

—

2.9

—

3.3

—

3.5

ns

Clock to Output Invalid

tKQX

1.0

—

1.0

—

1.0

—

1.0

—

1.0

—

1.0

—

ns

Clock to Output in Low-Z

tLZ1

1.0

—

1.0

—

1.0

—

1.0

—

1.0

—

1.0

—

ns

Setup time

tS

1.3

—

1.3

—

1.4

—

1.5

—

1.5

—

1.5

—

ns

Hold time

tH

0.2

—

0.3

—

0.4

—

0.5

—

0.5

—

0.5

—

ns

Flow

Through

Clock Cycle Time

tKC

6.5

—

6.5

—

6.5

—

7.0

—

7.5

—

8.5

—

ns

Clock to Output Valid

tKQ

—

6.5

—

6.5

—

6.5

—

7.0

—

7.5

—

8.5

ns

Clock to Output Invalid

tKQX

3.0

—

3.0

—

3.0

—

3.0

—

3.0

—

3.0

—

ns

Clock to Output in Low-Z

tLZ1

3.0

—

3.0

—

3.0

—

3.0

—

3.0

—

3.0

—

ns

Setup time

tS

1.5

—

1.5

—

1.5

—

1.5

—

1.5

—

1.5

—

ns

Hold time

tH

0.5

—

0.5

—

0.5

—

0.5

—

0.5

—

0.5

—

ns

Clock HIGH Time

tKH

1.3

—

1.3

—

1.3

—

1.3

—

1.5

—

1.7

—

ns

Clock LOW Time

tKL

1.5

—

1.5

—

1.5

—

1.5

—

1.7

—

2

—

ns

Clock to Output in

High-Z

(x18/x36)

tHZ1

1.0

2.3

1.0

2.5

1.0

2.7

1.0

2.9

1.0

3.0

1.0

3.0

ns

Clock to Output in

High-Z

(x72)

tHZ1

1.0

2.6

1.0

2.7

1.0

2.8

1.0

2.9

1.0

3.0

1.0

3.0

ns

G to Output Valid

(x18/x36)

tOE

—

2.3

—

2.5

—

2.7

—

2.9

—

3.3

—

3.5

ns

G to Output Valid

(x72)

tOE

—

2.6

—

2.7

—

2.8

—

2.9

—

3.3

—

3.5

ns

G to output in Low-Z

tOLZ1

0

—

0

—

0

—

0

—

0

—

0

—

ns

G to output in High-Z

(x18/x36)

tOHZ1

—

2.3

—

2.5

—

2.7

—

2.9

—

3.0

—

3.0

ns

G to output in High-Z

(x72)

tOHZ1

—

2.6

—

2.7

—

2.8

—

2.9

—

3.0

—

3.0

ns

ZZ setup time

tZZS2

5

—

5

—

5

—

5

—

5

—

5

—

ns

ZZ hold time

tZZH2

1

—

1

—

1

—

1

—

1

—

1

—

ns

ZZ recovery

tZZR

20

—

20

—

20

—

20

—

20

—

20

—

ns

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