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參數(shù)資料
| 型號： | GS880F18T-14T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 14 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 310K |
| 代理商： | GS880F18T-14T |
Rev: 1.06 9/2000
22/22
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
GS880F18/361.00 11/1999J
Content
First Release of 880 F.
GS880F18/36T1.00
K880F18/36T1.02 1/2000L
Content
Changed Flow Through Read-Write Cycle Timing Diagram for
accuracy.
Changed order of TQFP Address Inputs to match pinout.
Changed order of TQFP DATA Input and Output pins to
match pinout.
New GSI Logo.
GS880F1836T Rev. 1.02 1/
2000L;
GS880F1836T Rev. 1.03 3/
2000N
Content
Changed all speed bin information (headings, references,
tables, ordering info..) to reflect 14 -10Mhz
GS880F1836T Rev. 1.03 1/
2000N;
GS880F1836T Rev. 1.04 3/
2000O
Content
Corrections to AC Electrical Characteristics Table -
GS880F1836T Rev. 1.04 3/
2000O; 880F1836_r1_05
Content/Format
Removed 150 MHz speed bin
Added 18 ns speed bin
Updated format to comply with Technical Publications
standards
880F18_r1_05;
880F18_r1_06
Content
Updated Capitance table—removed Input row and changed
Output row to I/O
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| GS880F32AT-5.5 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
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| GS880F32AT-6.5 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs |
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