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參數(shù)資料
| 型號： | GS880F18T-14T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 CACHE SRAM, 14 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 310K |
| 代理商： | GS880F18T-14T |
Rev: 1.06 9/2000
9/22
2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
W
R
W
R
X
CR
R
CW
CR
W
CW
W
CW
Simplified State Diagram with G
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
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