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參數(shù)資料
| 型號(hào)： | GS9025ACTM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Receiver |
| 中文描述： | 串行數(shù)字接收機(jī) |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 192K |
| 代理商： | GS9025ACTM |
GENNUM CORPORATION
522 - 75 - 00
11
G
Fig. 19 R
VCO
vs. VCO Centre Frequency
The recommended R
VCO
value for auto rate SMPTE 259M
applications is 365
.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN, SMPTE, and SS[2:0] pins (for further
details, see section 4, Auto/Manual Data Rate Select) In
addition, a manually selectable modulus 8 divider allows
operation at data rates as low as 30Mb/s.
When the input data stream is removed for an excessive
period of time (see AC electrical characteristics table),the
VCO frequency can drift from the previously locked
frequency to the limits shown in Table1.
2-3. Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function which maximizes the
input jitter tolerance of the PLL.
2-4. Charge Pump
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design insures that the output phase does not drift when
data transitions are sparse. This makes the GS9025A ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.
2-5. Loop Filter
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9025A increased immunity
to PCB board noise.
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL DESIGN
GUIDELINES
section.
Recommended
SMPTE259M applications are shown in the Typical
Application Circuit.
values
for
3. FREQUENCY ACQUISITION
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9025A uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control
voltage so that the VCO frequency changes from -10% to
+10% of the centre frequency. Figure 20 shows a typical
sweep waveform.
Fig. 20 Typical Sweep Waveform
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 3-bit counter.
TABLE 1: Frequency Drift Range (when PLL loses lock)
LOSES LOCK FROM
MIN (%)
MAX(%)
143Mb/s lock
-21
21
177Mb/s lock
-12
26
270Mb/s lock
-13
28
360 Mb/s lock
-13
24
540 Mb/s lock
-13
28
0
100
200
300
400
500
600
700
800
0
200
400
600
800
1000
1200 1400
1600
1800
V
R
VCO
(
)
H
L
SMPTE=1
SSO=1
V
LF
t
swp
T
cycle
T
cycle
= t
swp
+ t
sys
t
sys
A
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