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參數(shù)資料
| 型號： | GS9025ACTM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Serial Digital Receiver |
| 中文描述： | 串行數(shù)字接收機 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 192K |
| 代理商： | GS9025ACTM |
GENNUM CORPORATION
522 - 75 - 00
13
G
The GS9025A defines the presence of input data when at
least one data transition occurs every 1μs.
The GS9025A assumes that it is NOT locked to a harmonic
if the pattern
‘
101
’
or
‘
010
’
(in the reclocked data stream)
occurs at least once every t
sys
/3 seconds. Using the
recommended component values, this corresponds to
approximately 150μs. In a harmonically locked system, all
bit cells are double clocked and the above patterns
become
‘
110011
’
and
‘
001100
’
, respectively.
5-1. Lock Time
The lock time of the GS9025A depends on whether the
input data is switching synchronously or asynchronously.
Synchronous switching refers to the case where the input
data is changed from one source to another source which is
at the same data rate (but different phase). Asynchronous
switching refers to the case where the input data is
changed from one source to another source which is at a
different data rate.
When input data to the GS9025A is removed, the GS9025A
latches the current state of the counter (divider modulus).
Therefore, when data is reapplied, the GS9025A begins the
lock procedure at the previous locked data rate. As a result,
in synchronous switching applications, the GS9025A locks
very quickly. The nominal lock time depends on the
switching time and is summarized in the Table 4.
In asynchronous switching applications, including power
up, the lock time is determined by the frequency acquisition
circuit (see section 3, Frequency Acquisition Circuit)
To acquire lock in manual mode, the frequency acquisition
circuit may have to sweep over an entire cycle depending
on initial conditions. Maximum lock time is 2T
cycle
+ 2t
sys
.
To acquire lock in auto tune mode, the frequency
acquisition circuit may have to cycle through 5 possible
counter states depending on initial conditions. Maximum
lock time is 6T
cycle
+ 2t
sys.
The nominal value of T
cycle
for the GS9025A operating in a
typical SMPTE 259M application is approximately 1.3ms.
The GS9025A has a dedicated LOCK output (pin 39)
indicating when the device is locked. It should be noted
that in synchronous switching applications where the
switching time is less than 0.5μs, the LOCK output will NOT
be de-asserted and the data outputs will NOT be muted.
6. OUTPUT DATA MUTING
The GS9025A internally mutes the SDO and SDO outputs
when the device is not locked. When muted, SDO/SDO are
latched providing a logic state to the subsequent circuit
and avoiding a condition where noise could be amplified
and appear as data.
The output data muting timing is shown in Figure 21.
Fig. 21 Output Data Muting Timing
7. CLOCK ENABLE
When CLK_EN is high, the GS9025A SCO/SCO outputs are
enabled. When CLK_EN is low, the SCO/SCO outputs are
tri-stated and float to V
CC
. Disabling the clock outputs
results in a power savings of 10%. It is recommended that
the CLK_EN input be hard wired to the desired state. For
applications which do not require the clock output, connect
CLK_EN to Ground and connect the SCO/SCO outputs to
V
CC
.
8. STRESSFULL DATA PATTERNS
All PLL's are susceptible to stressful data patterns which
can introduce bit errors in the data stream. PLL's are most
sensitive to patterns which have long run lengths of 0's or
1's (low data transition densities for a long period of time).
The GS9025A is designed to operate with low data
transition densities such as the SMPTE 259M pathological
signal (data transition density = 0.05).
9. PLL DESIGN GUIDELINES
The reclocking performance of the GS9025A is primarily
determined by the PLL. Thus, it is important that the system
designer is familiar with the basic PLL design equations.
A model of the GS9025A PLL is shown in Figure 22. The
main components are the phase detector, the VCO, and the
external loop filter components.
TABLE 4.
SWITCHING TIME
LOCK TIME
<0.5μs
10μs
0.5μs - 10ms
2t
sys
>10ms
2T
cycle
+ 2t
sys
LOCK
DDI
SDO
VALID
DATA
NO DATA TRANSITIONS
VALID
DATA
OUTPUTS MUTED
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS9028CKA | 制造商:Gennum Corporation 功能描述: |
| GS9028-CKA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
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