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參數(shù)資料
| 型號(hào)： | GT-64012 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器) |
| 中文描述： | 二級(jí)高速緩存控制器（用于MIPS的R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器的MIPS R4600/4650/4700/5000） |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 614K |
| 代理商： | GT-64012 |
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Tag
SRAM
Cache
Data
SRAM
External Agent
(System Controller)
GT-64012
QS3383
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ExtReq*
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Tag
Secondary Cache Address
TagOp[1:0]
VIMux
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GRdRdy*
GExtReq*
GRelease*
SCAdv*, SCAdS*
SCDOE*, SCDWr*
Valid
SCTReset*
SCTWr*
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SCALE*
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QS3383
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64-BIT MIPS PROCESSOR
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- 256KByte
- 512KByte
Fixed line size
- 4 double-words (32 bytes)
Write-through policy
Direct mapping
Physical address and tag
Zero wait-states for cache hit
Supports industry standard synchronous burst SRAMs
- 32Kx18
- 64Kx18
- 32Kx36
Moderate Data SRAM speed required
- 12ns for 50MHz
Supports de-facto standard cache tags
- 8Kx8 tag (IDT71B74)
- 16Kx15 tag (IDT71215)
Read burst latency of 3-1-1-1
Supports all write patterns (DDDD or slower)
Supports the R4700’s special write modes
- Pipeline
- Re-issue
“Transparent” architecture
- Design with no logic changes into existing systems
Easy evaluation via Galileo-2 CPU module
- Fits into existing CPU sockets with no board
changes to R4600/R4700 system
Compatible with Galileo GT-64010 System Controller
Minimizes use of external logic components
- Only 4 standard logic components needed besides
memory
Simple way to boost CPU performance
- Typical improvement range of 20%-100% depend-
ing on system architecture and code
5 Volt operation
- Easy to incorporate into a 3.3V environment
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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