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參數(shù)資料
| 型號(hào)： | GT-64012 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器) |
| 中文描述： | 二級(jí)高速緩存控制器（用于MIPS的R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器的MIPS R4600/4650/4700/5000） |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 614K |
| 代理商： | GT-64012 |
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Reset* initializes the internal state of the GT-64012. It does not initialize the Tag RAM entries. The configuration pin
(HitDly) is sampled during reset to determine whether to have zero or one wait-state in read hit cycles. This is designed
to accommodate Rev. 1.7 versions of the R4600. The pin is sampled during the last four TClk cycles in which Reset* is
asserted. When HitDly is sampled HIGH, there is one wait-state during read hits to support Rev. 1.7 R4600’s. When
HitDly is sampled LOW, there are no wait-states on read hits. Reset* and TClk must be connected to the CPU Reset
input and TClk output.
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Block Read Request
In a block read request and a hit in the secondary cache, the data will be supplied from the cache and the GT-64012
will not forward the request to the system interface (GValidOut* is not asserted).
In a miss in the secondary cache, the GT-64012 forwards the request to the system by asserting GValidOut* and
GRelease* two TClks after receiving the request from the CPU. The address and the command, which are no longer
available from the CPU, are driven onto the SysAD and SysCmd buses from the bi-directional latches (16501), by
means of the GT-64012 asserting SCOE*. When the data is returned from the system to the CPU, the GT-64012 writes
the line into the secondary cache (performs a line fill).
Uncached Read Requests
In an uncached read request the GT-64012 forwards the request to the system one TClk cycle after receiving the
request. When the system returns the data, the GT-64012 forwards it to the CPU without writing it to the secondary
cache.
Block Write Request
In a block write request the GT-64012 forwards the request to the system by asserting GValidOut* in the same TClk
the request is issued by the CPU (ValidOut* is asserted). Concurrently the GT-64012 writes the line to the cache and
updates the tag and Valid bit in the Tag RAM. The GT-64012 supports all write patterns of the R4600 (DDDD,
DXDXDXDX, etc.).
Uncached Write Request
In an uncached write request, the GT-64012 forwards the request to the system in the same TClk that the request is
issued from the CPU. The cache is not updated.
Flush
The CPU can flush the secondary cache by executing an uncached read request with TagOp0 LOW and TagOp1
HIGH. The GT-64012 will not forward this cycle to the system bus. It will reset the entire Tag RAM and return undefined
data to the CPU three TClks from ValidOut*. This means that the entire Tag RAM is cleared (flushed).
Cache Entry Invalidate
The CPU can invalidate an entry in the secondary cache Tag RAM by performing an uncached read with TagOp0
HIGH and TagOp1 LOW. The entry pointed by the address on SysAD[5:17/18] will be invalidated (17 or 18 as a function
of the size of the data SRAMs used). Note that both Flush and Cache Entry Invalidate operations return undefined
data. The GT-64012 always drives SysCmd[4] to check parity. Thus if the system is parity-protected, the CPU’s parity
checking should be turned off when executing cache operations.
External Requests
The GT-64012 supports external write requests and external null requests. It does not support external read
requests. All external requests are forwarded to the CPU without GT-64012 intervention.
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相關(guān)代理商/技術(shù)參數(shù) |
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| GT-64120A-B2 | 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA |
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