參數(shù)資料
型號(hào)： GT-64012
廠商： Galileo Technology Services, LLC
英文描述： Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器)
中文描述： 二級(jí)高速緩存控制器（用于MIPS的R4600/4650/4700/5000處理器的二級(jí)高速緩存控制器的MIPS R4600/4650/4700/5000）
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 614K
代理商： GT-64012
6HFRQGDU\ &DFKH &RQWUROOHU IRU 5
$OO GULYH VWUHQJWKV LQ SDUHQWKHVHV HJ P$ UHIHU WR WKH RULJLQDO *7 DV RSSRVHG WR WKH QHZ *7$
GRdRdy*
TClk
I
System Read Ready: When asserted by the system con-
troller, it indicates that the system can accept a CPU
Read request.
GRelease*
TClk
O
20mA
(32mA)
System Release: In response to the assertion of GEx-
tReq* or a CPU Partial Read or Block Read Miss, the GT-
64012 asserts GRelease*, signaling to the system con-
troller that the System interface is available.
GValidIn*
TClk
I
System Valid In: Asserted when the system controller
drives valid address or data onto the SysAD bus and valid
data identifier onto the SysCmd bus, during CPU Reads
or external requests.
GValidOut*
(1)
O
20mA
(32mA)
System Valid Out: Indicates to the system controller that
the CPU or the GT-64012 is driving a valid address or
data onto the SysAD bus and a valid command or data
identifier onto the SysCmd bus.
GWrRdy*
I
System Write Ready: Indicates that the system control-
ler can accept a CPU Write request.
SCOE*
TClk
O
12mA
(32mA)
Secondary Cache Output Enable: Provides output
enable control of the external bidirectional latches
(FCT16501). Active during Partial Reads and Block Read
Misses to drive address and command onto the system
controller.
Cache Interface
SCALE
(2)
O
8mA
(32mA)
Secondary Cache Address Latch Enable: Provides
latch enable control to the external bidirectional latches
(FCT16501). It is used to latch the address and command
at issue.
Hit
TClk
I
Hit: Indicates a valid match in the Tag RAM.
Valid
TClk
O
2mA
(32mA)
Valid: Validates tag entry during Block Write and Block
Read Miss (line fill). Invalidates tag entry during Tag Inval-
idate operation.
SCTReset*
TClk
O
2mA
(32mA)
Secondary Cache Tag Reset: A reset signal to the Tag
RAM, asserted during a Tag Flush operation.
SCTWr*
TClk
O
2mA
(32mA)
Secondary Cache Tag Write: Controls writes to the Tag
RAM.
SCDWr*
TClk
O
12mA
(32mA)
Secondary Cache Data Write: Enables data Writes to
the cache data SRAMs. Activated during Block Write and
Block Read Miss (line fill).
SCDOE*
TClk
O
12mA
(32mA)
Secondary Cache Data Output Enable: Enables data
output from the cache data SRAMs. Activated during
Block Read Hit.
SCAdv*
TClk
O
12mA
(32mA)
Secondary Cache Advance: Synchronously advances
the cache data SRAM internal burst address.
SCAdS*
(3)
O
16mA
(32mA)
Secondary Cache Address Strobe: Synchronously
latches the burst start address in the cache data SRAMs.
Pin name
Sync to
Type
Drive
Description
相關(guān)PDF資料
PDF描述
GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs(用于RC4640, RM523X和 VR4300 CPUs的系統(tǒng)控制器)
GT-96100A Advanced Communication Controller That Handles a Wide Range of Serial Communication Protocols,such as Ethernet,Fast Ethernet,and HDLC(通信協(xié)議的高級(jí)通信協(xié)議（以太網(wǎng)、快速以太網(wǎng)、HDLC）控制器)
GT5-2/1S-HU RECTANGULAR CONNECTOR
GT5-1S-HU(A) RECTANGULAR CONNECTOR
GT5-1S-HU(B) RECTANGULAR CONNECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT64115-A2-PBB-C000 制造商:Marvell 功能描述: 制造商:Marvell 功能描述:Marvell GT64115-A2-PBB-C000
GT-64120A-B-0 制造商:GALILEO 功能描述:
GT-64120A-B2 制造商:GALILEO 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Galileo Corp 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA 制造商:Marvell 功能描述:MULTIFUNCTION PERIPHERAL, 388 Pin Plastic BGA
GT64120AB2-BBB1C000 制造商:Marvell 功能描述:64-BIT MIPS SYSTEM CONTROLLER W/ 2 X 32-BIT OR 1 X 64-BIT/6 - Trays
GT64120AB2-BBB1C083 制造商:Marvell 功能描述:Marvell GT64120AB2-BBB1C083
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*