參數(shù)資料
型號(hào)： H8250
廠商： Electronic Theatre Controls, Inc.
英文描述： Universal Asynchronous Receiver/Transmitter
中文描述： 通用異步接收器/發(fā)送器
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 49K
代理商： H8250
CAST H8250 Megafunction Datasheet
CAST, Inc.
Page 2
Pin Description
Name
MR
CLK
RCLK
RD
WR
CS
DIN[7:0]
CTSn
DSRn
DCDn
SIN
RIn
A[2:0]
DOUT[7:0]
SOUT
DDIS
RTSn
DTRn
OUT1n
OUT2n
INTR
BAUDOUTn
RXRDY
TXRDY
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Polarity
High
-
-
High
Falling
High
-
Low
Low
Low
-
Low
-
-
-
High
Low
Low
Low
Low
High
Low
Low
Low
Description
Master Reset (Asynchronous)
Master clock (Should be Global Signal)
Receiver clock (Recommended as Global Signal)
Read control
Write control (Recommended as Global Signal)
Chip Select
Data Input Bus
Clear-to -Send
Data Set Ready
Data Carrier Detect
Serial Input Data
Ring Indicator
Register Select
Data Output Bus
Serial Output Data
Driver Disable
Request-to-Send
Data Terminal Ready
Output 1
Output 2
Interrupt pending
Baud Out
Receiver Ready to Receive Transmissions
Transmitter Ready to Transmit Data
Register Description
A(2:0)
Divisor *
Latch
Access Bit
0
0
1
1
0
X
X
X
X
X
X
Name
Symbol
Default
(reset)
value
XX
XX
01h
00h
00h
01h
00h
00h
60h
00h
00h
No.
bits
Read/
Write
0
0
0
1
1
2
3
4
5
6
7
Receiver Buffer Register
Transmitter Holding Register
Divisor Latch (LSB)
Divisor Latch (MSB)
Interrupt Enable Register
Interrupt Identification Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register
RBR
THR
DLR
DMR
IER
IIR
LCR
MCR
LSR
MSR
SR
8
8
8
8
8
8
8
8
8
8
8
R
W
R/W
R/W
R/W
R
R/W
R/W
R
R
R/W
*DLAB is the MSB of the Line Control Register
Sw itching Characteristics
Register W rite
The Address (A) and Chip Select (CS) signals are not latched and therefore must be valid throughout the write
process. Writing is done at the falling edge of the WR signal.
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