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參數(shù)資料
| 型號： | H8250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Universal Asynchronous Receiver/Transmitter |
| 中文描述： | 通用異步接收器/發(fā)送器 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 49K |
| 代理商： | H8250 |
CAST H8250 Megafunction Datasheet
CAST, Inc.
Page 3
A
valid
CS
WR
DIN
valid
Register Read
The Address (A) and Chip Select (CS) signals are not latched and therefore must be valid throughout the read
process. The RD signal is active 1.
A
valid
CS
RD
DOUT
DDIS
valid
W rite to Transmitter
The timing diagram below depicts the situation where the transmitter is in the process of transmitting a byte
which is made up of the Data, Parity and Stop bits. Once the byte is written into the Transmitter Holding
Register, the TXRDY signal goes into the off (or high) state. This means that the transmitter is ready for a
transfer. As the byte just written starts the transmission (with the Start bit) the TXRDY bit goes low showing
that the transmitter is ready for the next byte.
SOUT
WR
DATA
PARITY
STOP
START
TXRDY
Timing Information for Write Function
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