3550.6 February 8, 2006 Referring to Figure 10, both inputs are terminated in their characteristic impedance; 75 is typical for video applicati" />
參數(shù)資料
型號(hào): HA5024IBZ
廠商: Intersil
文件頁數(shù): 16/16頁
文件大?。?/td> 0K
描述: IC OPAMP QUAD 125MHZ 20-SOIC
標(biāo)準(zhǔn)包裝: 38
應(yīng)用: 電流反饋
電路數(shù): 4
-3db帶寬: 125MHz
轉(zhuǎn)換速率: 350 V/µs
電流 - 電源: 7.5mA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): ±4.5 V ~ 18 V
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
產(chǎn)品目錄頁面: 1234 (CN2011-ZH PDF)
9
3550.6
February 8, 2006
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 75
is typical for video
applications. Since the drivers usually are terminated in their
characteristic impedance the input gain is 0.5, thus the
amplifiers, U2, are configured in a gain of +2 to set the circuit
gain equal to one. Resistors R2 and R3 determine the amplifier
gain, and if a different gain is desired R2 should be changed
according to the equation G = (1 + R3/R2). R3 sets the
frequency response of the amplifier so you should refer to the
manufacturers data sheet before changing its value. R5, C1
and D1 are an asymmetrical charge/discharge time circuit
which configures U1 as a break before make switch to prevent
both amplifiers from being active simultaneously. If this design
is extended to more channels the drive logic must be designed
to be break before make. R4 is enclosed in the feedback
loop of the amplifier so that the large open loop amplifier
gain of U2 will present the load with a small closed loop
output impedance while keeping the amplifier stable for all
values of load capacitance.
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved.The frequency and gain
characteristics of the circuit are now those of the amplifier
independent of any multiplexing action; thus, problem two
has been solved. The multiplexer transition time is
approximately 15
s with the component values shown.
INPUT B
+
-
-5V
+
-
+5V
INHIBIT
CHANNEL
SWITCH
INPUT A
R1A
75
R1B
75
D1A
1N4148
U1C
U1A
U1B
U1D
R6
100K
R5A
2000
C1A
0.047
F
R5B
2000
D1B
1N4148
R1A
681
1
2
3
4
16
R3A
681
R4A
27
0.01
F
R2B
681
R4B
27
R3B
681
0.01
F
OUTPUT
7
6
5
13
10
U2B
U2A
C1B
0.047
F
NOTES:
22. U2: HA5022/24.
23. U1: CD4011.
FIGURE 10. LOW IMPEDANCE MULTIPLEXER
100
(NOTE 17)
100
(NOTE 17)
HA5024
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