參數(shù)資料
型號(hào)： HB288032MM1
元件分類： PROM
英文描述： FLASH 2.7V PROM CARD, XMA7
封裝： CARD-7
文件頁(yè)數(shù)： 27/80頁(yè)
文件大?。?/td> 236K
代理商： HB288032MM1
HB288032MM1
33
The data stream contains the net payload data (and error correction bits if an off-card ECC is used). The
data stream ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The
payload for block-oriented data transfer is preserved by a CRC check sum (refer to Chapter “Cyclic
Redundancy Check (CRC)”).
Stream read
There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11). This
command instructs the card to send its payload, starting at a specified address, until the host sends a
STOP_TRANSMISSION command (CMD12). The stop command has an execution delay due to the serial
command transmission. The data transfer stops after the end bit of the stop command. If the end of the
memory range is reached while sending data and no stop command has been sent yet by the host, the
contents of the further transferred payload is undefined. The maximum clock frequency for stream read
operation is given by the following formula:
max. speed = min (TRAN_SPEED, (8*2
READ_BL_LEN-NSAC)/TAAC),
these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the
card may not be able to sustain data transfer. If this happens, the card will set the UNDERRUN error bit in
the status register, abort the transmission and wait in the data state for a stop command.
Block read
The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BLK_LEN).
READ_BLK_PARTIAL is set, thus smaller blocks whose starting and ending address are wholly contained
within one physical block (as defined by READ_BLK_LEN) may also be transmitted. A CRC is appended
to the end of each block ensuring data transfer integrity. READ_SINGLE_BLOCK (CMD17) starts a
block
read
and
after
a
complete
transfer
the
card
goes
back
to
Transfer
State.
READ_MULTIPLE_BLOCK (CMD18) starts a transfer of several consecutive blocks. Blocks will be
continuously transferred until a stop is issued.
Stream write
Stream write (CMD20) starts the data transfer from the host to the card beginning from the starting address
until the host issues a stop command.
If partial blocks are allowed (if CSD parameter
WRITE_BL_PARTIAL is set) the data stream can start and stop at any address within the card address
space, otherwise it shall start and stop only at block boundaries. Since the amount of data to be transferred
is not determined in advance, CRC can not be used. If the end of the memory range is reached while
sending data and no stop command has been sent by the host, all further transferred data is discarded. The
maximum clock frequency for stream write operation is given by the following formula:
max. speed = min ( TRAN_SPEED, (8*2WRITE_BL_LEN-NSAC)/(TAAC*R2W_FACTOR)),
these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the
card may not be able to process the data and will stop programming, set the OVERRUN error bit in the
status register, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop
command. The write operation shall also be aborted if the host tries to write over a write-protected area. In
this case, however, the card shall set the WP_VIOLATION bit.
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