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參數(shù)資料
| 型號(hào)： | HB288032MM1 |
| 元件分類： | PROM |
| 英文描述： | FLASH 2.7V PROM CARD, XMA7 |
| 封裝： | CARD-7 |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HB288032MM1 |
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HB288032MM1
50
SPI Communication
The SPI mode consists of a secondary communication protocol.
This mode is a subset of the
MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s
(and lately a few other vendors’) microcontrollers. The interface is selected during the first reset command
after power up (CMD0) and cannot be changed once the part is powered on. The SPI standard defines the
physical link only, and not the complete data transfer protocol. The MultiMediaCard SPI implementation
uses a subset of the MultiMediaCard protocol and command set. It is intended to be used by systems which
require a small number of card (typically one) and have lower data transfer rates (compared to
MultiMediaCard protocol based systems). From the application point of view, the advantage of the SPI
mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to minimum. The
disadvantage is the loss of performance of the SPI system versus MultiMediaCard (lower data transfer rate,
fewer cards, hardware CS per card etc.). While the MultiMediaCard channel is based on command and
data bitstreams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte
oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the
length is a multiple of 8 clock cycles). Similar to the MultiMediaCard protocol, the SPI messages consist
of command, response and data-block tokens (refer to Chapter “Commands” and Chapter “Responses” for
a detailed description). All communication between host and cards is controlled by the host (master). The
host starts every bus transaction by asserting the CS signal low. The response behavior in the SPI mode
differs from the MultiMediaCard mode in the following three aspects:
The selected card always responds to the command.
An additional (8 bit) response structure is used
When the card encounters a data retrieval problem, it will respond with an error response (which
replaces the expected data block) rather than by a time-out as in the MultiMediaCard mode.
Only single block read write operations are supported in SPI mode. In addition to the command response,
every data block sent to the card during write operations will be responded with a special data response
token. A data block may be as big as one card sector and as small as a single byte. Partial block read/write
operations are enabled by card options specified in the CSD register.
Mode Selection
The MultiMediaCard wakes up in the MultiMediaCard mode. It will enter SPI mode if the CS signal is
asserted (negative) during the reception of the reset command (CMD0). If the card recognizes that the
MultiMediaCard mode is required it will not respond to the command and remain in the MultiMediaCard
mode. If SPI mode is required the card will switch to SPI and respond with the SPI mode R1 response.
The only way to return to the MultiMediaCard mode is by entering the power cycle. In SPI mode the
MultiMediaCard protocol state machine is not observed. All the MultiMediaCard commands supported in
SPI mode are always available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HB288064A5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:FLASH ATA Card |
| HB288064A6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:FLASH ATA Card |
| HB288064C5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:CompactFlash⑩ |
| HB288064C6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:CompactFlash⑩ |
| HB288064MM1 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:MultiMediaCard 64 MByte |
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