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參數(shù)資料
| 型號： | HC1-55564-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Voltage Regulator IC; Output Current:1A; Output Voltage Max:125.8V; Output Voltage Min:124.2V |
| 中文描述： | CVSD, CVSD CODEC, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 69K |
| 代理商： | HC1-55564-9 |
2
HC-55564
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to V
DD
0.3V
Maximum V
DD
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0V
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Operating Conditions
Temperature Range
HC-55564-5, -7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to 75
0
C
HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
0
C
HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
0
C
Operating V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
θ
JA
(
o
C/W)
70
85
98
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Die Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V
DD
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, typical parameters are at 25
o
C, Min-Max are over operating temperature
ranges. V
DD
= 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, A
IN
= 1.2V
RMS
PARAMETER
SYMBOL
CLK
I
DD
V
IH
V
IL
V
OH
V
OL
CONDITIONS
MIN
9
-
3.5
-
4.0
-
30
-
-
-
-
-2.0
-
1.0
TYP
16
0.3
-
-
-
-
-
0.5
0.5
280
150
-
4.0
-
MAX
64
1.5
-
1.5
-
0.4
70
1.2
1.2
-
-
+2.0
-
-
UNITS
kbps
mA
V
V
V
V
%
V
RMS
V
RMS
k
k
dB
ms
ms
Sampling Rate
Supply Current
Logic ‘1’ Input
Logic ‘0’ Input
Logic ‘1’ Output
Logic ‘0’ Output
Clock Duty Cycle
Audio Input Voltage
Audio Output Voltage
Audio Input Impedance
Audio Output Impedance
Transfer Gain
Syllabic Filter Time Constant
Signal Estimate Filter Time
Constant
Enc Threshold
Minimum Step Size
Quieting Pattern Amplitude
AGC Threshold
Clamping Threshold
NOTES:
2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.
3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V
DD
or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive one LS TTL load.
5. Recommended voice input range for best voice performance. Should be externally AC coupled.
6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by
±
2dB.
7. Presents series impedance with audio signal. Zero signal reference is approximately V
DD
/2.
8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.
9. The minimum audio input voltage above which encoding takes place.
10. The minimum audio output voltage change that can be produced by the internal DAC.
11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.
12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
V
DD
/2
±
25% of V
DD
.
13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-
scale value, and will unclamp when it falls below this value (positive or negative).
Note 2
Note 3
Note 3
Note 4
Note 4
A
IN
A
OUT
Z
IN
Z
OUT
A
E-D
t
SF
t
SE
AC Coupled (Note 5)
AC Coupled (Note 6)
Note 7
Note 7
No Load, Audio In to Audio Out.
Note 8
Note 8
AIN at 100Hz (Note 9), (Typ) 0.3% = 15mV
RMS
Note 10
FZ = 0V or APT = 0V (Note 11)
Note 12
Note 13
-
-
-
-
-
6
-
-
-
-
-
mV
PEAK
%V
DD
mV
P-P
F.S.
F.S.
MSS
V
QP
V
ATH
V
CTH
0.1
10
0.1
0.75
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