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參數(shù)資料
| 型號(hào)： | HC1-55564-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Voltage Regulator IC; Output Current:1A; Output Voltage Max:125.8V; Output Voltage Min:124.2V |
| 中文描述： | CVSD, CVSD CODEC, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | HC1-55564-9 |
4
HC-55564
Timing Waveforms
FIGURE 2. CVSD TIMING DIAGRAM
0
1
1
0
SAMPLING CLOCK
FZ/APT
DEC/ENC
DIGITAL NRZ IN
DIGITAL NRZ OUT
t
DS
0
1
1
t
DS
: DATA SET UP TIME 100ns TYPICAL
CVSD Hookup for Evaluation
The circuit in Figure 3 is sufficient to evaluate the voice qual-
ity of the CVSD, since when encoding, the feedback signal at
the audio output pin is the reconstructed audio input signal.
CVSD design considerations are as follows:
1. Care should be taken in layout to maintain isolation
between analog and digital signal paths for proper noise
consideration.
2. Power supply decoupling is necessary as close to the
device as possible. A 0.1
μ
F should be sufficient.
3. Ground, then power, must be present before any input sig-
nals are applied to the CVSD. Failure to observe this may
cause a latchup condition which may be destructive.
Latchup may be removed by cycling the power off/on. A
power-up reset circuit may be used that strobes Force
Zero (Pin 13) during power-up as follows:
4. Analog (signal) ground (Pin 2) should be externally tied to
Digital GND (Pin 8) and power supply ground. It is recom-
mended that the A
IN
and A
OUT
ground returns connect
only to Pin 2.
5. Digital inputs and outputs are compatible with standard
CMOS logic using the same supply voltage. All unused
logic inputs must be tied to the appropriate logic level for
desired operation. It is recommended that unused inputs
tied high be done so through a pull-up resistor (1k
to
10k
). TTL outputs will require 1k
pull-up resistors. Pins
4 and 14 will each drive CMOS logic or one low power TTL
input.
6. Since the Audio Out pins are internally DC biased to V
DD
/2,
AC coupling is required. In general, a value of 0.1
μ
F is suffi-
cient for AC coupling of the CVSD audio pins to a filter circuit.
7. The AGC output may be externally integrated to drive an
AGC pre-amp, or it could drive an LED indicator through a
buffer to indicate proper speaking volume.
V
DD
R
C
(13)
FZ
Interface Circuit for HC-55564 CVSD
(DIP Pin Numbers Shown)
AUDIO SOURCE
INPUT
LEVEL ADJUST
R
C
R
A
, R
B
, C
A
OPTIONAL
R
A
C
A
R
B
VF
X
1+
VF
X
1-
GS
X
VF
R
0
PWRI
V
CC
V
BB
GNDD
CLK
PDN
CLK0
VF
R
I
VF
X
0
PWR0+
AUDIO OUT
TP3040
HC-55564
CLK GEN
EXTERNAL
CONTROL
DIGITAL
GND
ANALOG
GND
CLK
V
DD
A
OUT
A
IN
AGC
D
OUT
D
IN
FZ
APT
E/D
(TO DATA I/F)
(FROM DATA I/F)
EXTERNAL
CONTROL
GNDA
1
2
3
4
9
8
5V
-5V
0.1
μ
0.1
μ
15
12
0.1
μ
0.1
μ
5
3
1
R
D
(NOTE)
11
13
14
10
16
6
0.1
μ
8
÷
n
9
2
10
11
13
12
14
4
NOTE: R
D
= 100k
to 1M
5
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