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參數(shù)資料
| 型號： | HC1-55564-9 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | Voltage Regulator IC; Output Current:1A; Output Voltage Max:125.8V; Output Voltage Min:124.2V |
| 中文描述： | CVSD, CVSD CODEC, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 69K |
| 代理商： | HC1-55564-9 |
5
HC-55564
Figures 4, 5, and 6 illustrate the typical frequency
response of the HC-55564 for varying input levels and for
varying sampling rates. To prevent slope overload (slew
limiting), the 0dB boundary should not be exceeded. The
frequency response is directly proportional to the sampling
clock rate. The flat bandwidth at 0dB doubles for every
doubling in sampling rate. The output levels were mea-
sured in the encode mode, without filtering, from A
IN
to
A
OUT
, at V
DD
= 5V. 0dB = 1.2V
RMS
.
FIGURE 4. 16kbps
FIGURE 5. 32kbps
FIGURE 6. 64kbps
INPUT FREQUENCY AT A
IN
(Hz)
A
OUT
A
IN
-36dB
-30dB
-24dB
-18dB
-12dB
-6dB
0dB = INPUT SIGNAL LEVEL
100
1000
-40
-30
-20
-10
d
10000
INPUT FREQUENCY AT A
IN
(Hz)
100
1000
-40
-30
-20
-10
d
10000
A
OUT
A
IN
-36dB
-30dB
-24dB
-18dB
-12dB
-6dB
0dB = INPUT SIGNAL LEVEL
INPUT FREQUENCY AT A
IN
(Hz)
100
1000
-40
-30
-20
-10
d
10000
-36dB
-30dB
-24dB
-18dB
-12dB
-6dB
0dB = INPUT SIGNAL LEVEL
A
OUT
A
IN
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