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參數(shù)資料
| 型號： | HC4052 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | T-PNP SI-AF PO |
| 中文描述： | 雙4通道模擬多路復用器/解復用器 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 341K |
| 代理商： | HC4052 |
MC74VHC4051, MC74VHC4052, MC74VHC4053
http://onsemi.com
6
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
VCC
Guaranteed Limit
Symbol
Parameter
VCC
V
–55 to 25
°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin
Maximum Input Capacitance, Channel–Select or Enable Inputs
10
pF
CI/O
Maximum Capacitance
Analog I/O
35
pF
(All Switches Off)
Common O/I: VHC4051
VHC4052
VHC4053
130
80
50
130
80
50
130
80
50
Feedthrough
1.0
Typical @ 25
°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Figure 13)*
VHC4051
VHC4052
VHC4053
45
80
45
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
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