L
G
R
List of Figures
General Release Specification
MC68HC908AT32
—
Rev. 2.0
34
List of Figures
MOTOROLA
Figure
Title
Page
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
Transmit Buffer Priority Register (TBPR) . . . . . . . . . . . . . .421
MSCAN08 Control Register Structure . . . . . . . . . . . . . . . .422
Module Control Register 0 (CMCR0) . . . . . . . . . . . . . . . . .424
Module Control Register (CMCR1) . . . . . . . . . . . . . . . . . .426
Bus Timing Register 0 (CBTR0). . . . . . . . . . . . . . . . . . . . .427
Bus Timing Register 1 (CBTR1). . . . . . . . . . . . . . . . . . . . .428
Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . . . .430
Receiver Interrupt Enable Register (CRIER) . . . . . . . . . . .432
Transmitter Flag Register (CTFLG) . . . . . . . . . . . . . . . . . .433
Transmitter Control Register (CTCR). . . . . . . . . . . . . . . . .435
Identifier Acceptance Control Register (CIDAC) . . . . . . . .436
Receiver Error Counter (CRXERR) . . . . . . . . . . . . . . . . . .437
Transmit Error Counter (CTXERR) . . . . . . . . . . . . . . . . . .438
Identifier Acceptance Registers (CIDAR0–CIDAR3) . . . . .439
Identifier Mask Registers (CIDMR0–CIDMR3). . . . . . . . . .440
24-1
24-2
24-3
Keyboard Module Block Diagram. . . . . . . . . . . . . . . . . . . .445
Keyboard Status and Control Register (KBSCR). . . . . . . .449
Keyboard Interrupt Enable Register (KBIER). . . . . . . . . . .450
25-1
25-2
25-3
25-4
25-5
TIMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . .461
TIMA Status and Control Register (TASC). . . . . . . . . . . . .469
TIMA Counter Registers (TCNTH and TCNTL) . . . . . . . . .471
TIMA Counter Modulo Registers
(TAMODH and TAMODL) . . . . . . . . . . . . . . . . . . . . . . .472
TIMA Channel Status
and Control Registers (TACC0–TASC5). . . . . . . . . . . .473
CHxMAX Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478
TIMA Channel Registers
(TACH0H/L–TACH3H/L) . . . . . . . . . . . . . . . . . . . . . . . .479
25-6
25-7
25-8
26-1
26-2
26-3
26-4
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .485
ADC Status and Control Register (ADSCR). . . . . . . . . . . .489
ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . .492
ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . .492
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.