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參數(shù)資料
| 型號(hào)： | HCS112KMSR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Radiation Hardened Dual JK Flip-Flop |
| 中文描述： | HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| 封裝： | CERAMIC, DFP-16 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 180K |
| 代理商： | HCS112KMSR |
18
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HCS112MS
Spec Number
518830
Propagation Delay Timing Diagram and
Load Circuit
Transition Timing Diagram
VOLTAGE LEVELS
PARAMETER
HCS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
VS
INPUT
OUTPUT
VIH
VSS
VOH
VOL
TPLH
TPHL
VS
OUTPUT
TTHL
80%
20%
80%
20%
VOH
VOL
TTLH
DUT
TEST
POINT
RL
CL = 50pF
RL = 500
CL
Pulse Width, Setup, Hold Timing Diagram
Negative Edge Trigger and AC Load
Circuit
VOLTAGE LEVELS
PARAMETER
HCTS
UNITS
VCC
4.50
V
VIH
4.50
V
VS
2.25
V
VIL
0
V
GND
0
V
TW
TH
VS
TSU
INPUT
VIH
VIL
INPUT CP
VIH
VIL
TW
VS
TH = HOLD TIME
TSU = SETUP TIME
TW = PULSE WIDTH
DUT
TEST
POINT
RL
CL = 50pF
RL = 500
CL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HCS112MS | Dual JK Flip-Flop(雙J-K觸發(fā)器) |
| HCS112D | Radiation Hardened Dual JK Flip-Flop |
| HCS112DMSR | Radiation Hardened Dual JK Flip-Flop |
| HCS112K | Radiation Hardened Dual JK Flip-Flop |
| HCS112HMSR | Radiation Hardened Dual JK Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HCS112MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Dual JK Flip-Flop |
| HCS114-01GG | 制造商:Advanced Interconnect 功能描述: |
| HCS11DMSR | 制造商:Intersil Corporation 功能描述:AND GATE 3-ELEM 3-IN CMOS 14PIN SBCDIP - Rail/Tube |
| HCS11KMSR | 制造商:Intersil Corporation 功能描述:AND GATE 3-ELEM 3-IN CMOS 14CFPAK - Bulk |
| HCS11MS | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened Triple 3-Input AND Gate |
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